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[otbn,rtl] Fix timing on instruction memory request
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This stops errors factoring into the outputs for the instruction memory
request. Now on error the next imem request will still occur but OTBN
otherwise immediately halts are previously.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
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GregAC committed Jan 26, 2024
1 parent 6bac489 commit 69cbddb
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Showing 2 changed files with 7 additions and 4 deletions.
1 change: 0 additions & 1 deletion hw/ip/otbn/rtl/otbn_controller.sv
Original file line number Diff line number Diff line change
Expand Up @@ -490,7 +490,6 @@ module otbn_controller
// On any error immediately halt, either going to OtbnStateLocked or OtbnStateHalt depending on
// whether it was a fatal error.
if (err) begin
prefetch_en_o = 1'b0;
insn_fetch_resp_clear_o = 1'b1;

if (fatal_err) begin
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10 changes: 7 additions & 3 deletions hw/ip/otbn/rtl/otbn_instruction_fetch.sv
Original file line number Diff line number Diff line change
Expand Up @@ -102,8 +102,10 @@ module otbn_instruction_fetch
logic [NWdr-1:0] rf_bignum_wr_sec_wipe_onehot;

// The prefetch has failed if a fetch is requested and either no prefetch has done or was done to
// the wrong address.
assign insn_prefetch_fail = insn_fetch_req_valid_i &
// the wrong address. The `insn_fetch_req_valid_raw_i` signal doesn't factor in errors which is
// important to avoid timing issues here as this signal factors into the muxing for the
// imem_addr_o output.
assign insn_prefetch_fail = insn_fetch_req_valid_raw_i &
(~imem_rvalid_i || (insn_fetch_req_addr_i != insn_prefetch_addr));

// Fetch response is valid when prefetch has matched what was requested. Otherwise if no fetch is
Expand Down Expand Up @@ -315,7 +317,9 @@ module otbn_instruction_fetch
// By default prefetch the next instruction
imem_addr_o = insn_prefetch_addr + 'd4;

if (!insn_fetch_req_valid_i) begin
// Use the `insn_fetch_req_valid_raw_i` signal here as it doesn't factor in errors. This is
// important for timing reasons so errors don't factor into the `imem_addr_o` signal.
if (!insn_fetch_req_valid_raw_i) begin
// Keep prefetching the same instruction when a new one isn't being requested. In this
// scenario OTBN is stalled and will eventually want the prefetched instruction.
imem_addr_o = insn_prefetch_addr;
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