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vohoangnguyennnn/README.md
Vo Hoang Nguyen - Verilog | SystemVerilog | RISC-V
Typing SVG

Hi 👋, I'm Vo Hoang Nguyen

A Passionate Hardware & IC Design Engineer-in-training

Third-year student majoring in Electronics and Communications Engineering, focused on IC Design, CPU/SoC architecture, and AI-related hardware systems. I love digging into how silicon actually makes computers think — let's connect and build something together!

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👤 About Me

  • 🌱 Currently studying IC Design
  • 🚀 Diving deeper into CPU/SoC architecture and digital front-end design flows
  • 💡 Passionate about hardware design, CPU/SoC architecture, and AI-related hardware systems
  • 💬 Ask me about Digital Logic Design | Verilog/SystemVerilog | CPU Architecture
  • 🤝 Looking to collaborate on RISC-V / CPU / SoC front-end design projects
  • 📫 How to reach me: connect via the links below
 Circuit board animation

🛠️ Skills & Tools

Verilog SystemVerilog RISC--V C Python Linux Git

🌍 Connect with Me

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  1. riscv-rv32im-core riscv-rv32im-core Public

    5-stage pipelined RISC-V CPU core (RV32IM) written in SystemVerilog. Features forwarding, hazard detection, and minimal CSR support.

    SystemVerilog

  2. smart-parking-fpga-AI smart-parking-fpga-AI Public

    RTL-based smart parking controller with UART protocol, FPGA verification, ESP32 gateway and AI license plate recognition integration

    SystemVerilog 5 1

  3. spi-protocol spi-protocol Public

    Reusable SPI Master IP Core written in Verilog with configurable clock divider, CPOL/CPHA support, and self-checking verification environment.

    Verilog 1

  4. APB4-ip-framework APB4-ip-framework Public

    AMBA APB4 peripheral framework with reusable protocol logic, register bank, GPIO/Timer examples, and UVM verification.

    SystemVerilog

  5. Asynchronous-FIFO Asynchronous-FIFO Public

    Asynchronous FIFO design in SystemVerilog and testbench

    SystemVerilog

  6. fpga-video-stream-processor fpga-video-stream-processor Public

    Real-time video stream processing pipeline implemented on FPGA

    SystemVerilog