Clock domain annotation support

[dalance]

Migration guide

Add clock domain annotatins if there are some clocks in a module.
Add unsafe (cdc) blocks to boundaries between clock domains.

• From

module ModuleA (
    i_clk_a: input  clock,
    i_dat_a: input  logic,
    o_dat_a: output logic,
    i_clk_b: input  clock,
    i_dat_b: input  logic,
    o_dat_b: output logic,
) {
   // from i_clk_a domain to i_clk_b domain
   assign o_dat_b = i_dat_a;
}

• To

module ModuleA (
    i_clk_a: input  'a clock,
    i_dat_a: input  'a logic,
    o_dat_a: output 'a logic,
    i_clk_b: input  'b clock,
    i_dat_b: input  'b logic,
    o_dat_b: output 'b logic,
) {
    unsafe (cdc) {
        assign o_dat_b = i_dat_a;
    }
}

Description

This PR introduces clock domain annotation and unsafe (cdc) block to specify clock domain crossing explicitly.
By the annotation, Veryl compiler detects unexpected clock domain crossing which is not specified by unsafe (cdc).

Closes #713