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Merge pull request #717 from veryl-lang/fix_test_without_embed
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Fix test without embed
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dalance authored May 13, 2024
2 parents 6f26bfe + 564db9e commit c13bded
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Showing 6 changed files with 28 additions and 9 deletions.
12 changes: 6 additions & 6 deletions Veryl.lock
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Expand Up @@ -2,16 +2,16 @@
# It is not intended for manual editing.
[[projects]]
name = "veryl_sample1"
uuid = "ac7728ce-73f1-5fe1-a311-560b47c47cf2"
version = "0.11.0"
uuid = "7a8f66ee-ce45-56a4-aa67-647def541086"
version = "0.13.0"
url = "https://github.com/veryl-lang/sample"
revision = "bb28f79b87efd2feba2d0a22f6306855284f89ca"
revision = "8799cfb19e50f60c6103dda46fe98c1c712a5f8b"
dependencies = []

[[projects]]
name = "veryl_sample2"
uuid = "4d65038e-0712-5d63-9e2d-62618ea6ea0a"
version = "0.12.0"
uuid = "2d548dd9-6181-5cf7-9542-b60a737f6f72"
version = "0.14.0"
url = "https://github.com/veryl-lang/sample"
revision = "33ddf03c55b74e3d89a7f00a1afb69d8fa80f7ee"
revision = "bfe86a4a232752413b8d0e91f61f47c11a2db927"
dependencies = []
4 changes: 2 additions & 2 deletions Veryl.toml
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Expand Up @@ -26,6 +26,6 @@ compile_args = ["-full64"]

[dependencies]
"https://github.com/veryl-lang/sample" = [
{version = "0.11.0", name = "veryl_sample1"},
{version = "0.12.0", name = "veryl_sample2"},
{version = "0.13.0", name = "veryl_sample1"},
{version = "0.14.0", name = "veryl_sample2"},
]
1 change: 1 addition & 0 deletions crates/emitter/src/emitter.rs
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Expand Up @@ -1557,6 +1557,7 @@ impl VerylWalker for Emitter {
test_name
);
self.token(&arg.hash.hash_token.replace(&text));
self.newline();
self.attribute.push(AttributeType::Test);
}
}
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2 changes: 1 addition & 1 deletion std
11 changes: 11 additions & 0 deletions testcases/sv/48_test.sv
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Expand Up @@ -2,6 +2,7 @@ module veryl_testcase_Module48;
endmodule

`ifdef __veryl_test_veryl_testcase_test1__

module test1;
initial begin
$display("hello");
Expand All @@ -16,6 +17,7 @@ endmodule
`endif

`ifdef __veryl_test_veryl_testcase_test2__

module test2;
// parse error
initial
Expand All @@ -24,10 +26,19 @@ endmodule
`endif

`ifdef __veryl_test_veryl_testcase_test3__

module test3;
// elaborate error
tri logic a;
always_comb a = 1;
endmodule

`endif

`ifdef __veryl_test_veryl_testcase_test4__
module veryl_testcase_test4;
initial begin
$display("test4");
end
endmodule
`endif
7 changes: 7 additions & 0 deletions testcases/veryl/48_test.veryl
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Expand Up @@ -30,3 +30,10 @@ module test3;
always_comb a = 1;
endmodule
}}}

#[test(test4)]
module test4 {
initial {
$display("test4");
}
}

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