Merge pull request #1181 from taichi-ishitani/disable_port_default_va…

…lue_for_function

Temporarily disable port default value for function

crates/analyzer/src/handlers/check_port.rs

@@ -54,9 +54,15 @@ impl VerylGrammarTrait for CheckPort<'_> {
 
                 if let Some(x) = &x.port_type_concrete_opt0 {
                     let is_valid_port_default_value = match direction {
-                        Direction::Input(_) => true,
-                        Direction::Output(_) if !self.in_function => {
-                            is_anonymous_expression(&x.port_default_value.expression)
+                        Direction::Input(_) => {
+                            // For now, port default value is allowed for module only.
+                            // https://github.com/veryl-lang/veryl/issues/1178#issuecomment-2568996379
+                            !self.in_function
+                        }
+                        Direction::Output(_) => {
+                            // For SystemVerilog, output ports of a function cannot be released.
+                            !self.in_function
+                                && is_anonymous_expression(&x.port_default_value.expression)
                         }
                         _ => false,
                     };

crates/analyzer/src/tests.rs

@@ -767,6 +767,21 @@ fn invalid_port_default_value() {
         AnalyzerError::InvalidPortDefaultValue { .. }
     ));
 
+    let code = r#"
+    module ModuleA {
+        function FuncA(
+            a: input logic = 1,
+        ) {
+        }
+    }
+    "#;
+
+    let errors = analyze(code);
+    assert!(matches!(
+        errors[0],
+        AnalyzerError::InvalidPortDefaultValue { .. }
+    ));
+
     let code = r#"
     module ModuleA {
         function FuncA(

testcases/sv/73_port_default_value.sv

@@ -42,52 +42,4 @@ module veryl_testcase_Module73B;
 
     );
 endmodule
-
-module veryl_testcase_Module73C;
-    function automatic void __FuncC__0(
-        input logic i_a,
-        input logic i_b,
-        input logic i_c
-    ) ;
-    endfunction
-    function automatic void __FuncC__1(
-        input logic i_a,
-        input logic i_b,
-        input logic i_c
-    ) ;
-    endfunction
-
-    always_comb begin
-        __FuncC__0(veryl_testcase_Package73::A, 0, 1);
-        __FuncC__1(veryl_testcase_Package73::A, 1, 1);
-        __FuncC__1(0, 0, 1);
-    end
-endmodule
-
-module veryl_testcase_Module73D;
-    function automatic bit   __FuncD__0(
-        input logic i_a,
-        input logic i_b,
-        input logic i_c
-    ) ;
-        return 0;
-    endfunction
-    function automatic bit   __FuncD__1(
-        input logic i_a,
-        input logic i_b,
-        input logic i_c
-    ) ;
-        return 0;
-    endfunction
-
-    bit _d;
-    bit _e;
-    bit _f;
-
-    always_comb begin
-        _d = __FuncD__0(veryl_testcase_Package73::A, 0, 1);
-        _e = __FuncD__1(veryl_testcase_Package73::A, 1, 1);
-        _f = __FuncD__1(0, 0, 1);
-    end
-endmodule
 //# sourceMappingURL=../map/testcases/sv/73_port_default_value.sv.map

testcases/veryl/73_port_default_value.veryl

@@ -19,37 +19,3 @@ module Module73B {
         i_b: 0,
     );
 }
-
-module Module73C {
-    function FuncC::<B: const> (
-        i_a: input logic = Package73::A,
-        i_b: input logic = B           ,
-        i_c: input logic = 1           ,
-    ) {}
-
-    always_comb {
-        FuncC::<0>();
-        FuncC::<1>();
-        FuncC::<1>(0, 0);
-    }
-}
-
-module Module73D {
-    function FuncD::<B: const> (
-        i_a: input logic = Package73::A,
-        i_b: input logic = B           ,
-        i_c: input logic = 1           ,
-    ) -> bit {
-        return 0;
-    }
-
-    var _d: bit;
-    var _e: bit;
-    var _f: bit;
-
-    always_comb {
-        _d = FuncD::<0>();
-        _e = FuncD::<1>();
-        _f = FuncD::<1>(0, 0);
-    }
-}