Skip to content

Generalize Parmys Mult_Split to Allow for Multipliers Whose Input Widths are not Equal #3143

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 8 commits into
base: master
Choose a base branch
from
Open

Generalize Parmys Mult_Split to Allow for Multipliers Whose Input Widths are not Equal #3143

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
1788fe3
added check that would have made debuging easier
WhiteNinjaZ Jun 13, 2025
19653ee
fix multiplier
WhiteNinjaZ Jun 13, 2025
c713f85
new method, passing parmys
WhiteNinjaZ Jun 14, 2025
b900ffd
cleanup and clarified comments
WhiteNinjaZ Jun 16, 2025
da60450
Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…
WhiteNinjaZ Jun 16, 2025
d87e7e1
add tests and golden for reg_strong
WhiteNinjaZ Jun 16, 2025
1391852
Added mcml golden results to nightly
WhiteNinjaZ Jun 19, 2025
44782b5
Merge branch 'master' into fix_mult
WhiteNinjaZ Jun 20, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Merge branch 'master' into fix_mult
  • Loading branch information
@WhiteNinjaZ
WhiteNinjaZ authored Jun 20, 2025
commit 44782b5cca01d2e93c48195bdc720299a2c349c1
2 changes: 1 addition & 1 deletion ...low/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,4 +5,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem e
7series_BRAM_DSP_carry.xml bgm.v common 738.51 vpr 1.09 GiB -1 -1 23.62 654168 14 38.57 -1 -1 124128 -1 -1 -1 257 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 1147576 257 32 37283 34221 1 23859 3594 66 66 4356 CLB auto 369.5 MiB 486.01 1.42717e+06 292842 2727876 904302 1772661 50913 914.3 MiB 89.88 0.92 36.395 23.2057 -27798.9 -23.2057 23.2057 0.03 0.0420198 0.0365039 4.49405 3.75685 -1 -1 -1 -1 -1 405172 17 2.52497e+08 1.81881e+08 8.29171e+07 19035.1 37.75 5.87139 4.87957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
7series_BRAM_DSP_carry.xml stereovision0.v common 305.97 vpr 477.68 MiB -1 -1 4.47 103400 5 2.93 -1 -1 70128 -1 -1 -1 169 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 489148 169 197 23225 21365 1 9660 1645 42 42 1764 CLB auto 182.7 MiB 257.68 191242 69741 865479 231951 560905 72623 401.9 MiB 11.92 0.12 6.0701 4.03928 -16398 -4.03928 4.03928 0.01 0.0109682 0.00913863 1.16208 0.959963 -1 -1 -1 -1 -1 65287 12 9.88618e+07 6.89317e+07 3.28179e+07 18604.2 7.69 1.47609 1.21957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
7series_BRAM_DSP_carry.xml stereovision1.v common 329.87 vpr 834.59 MiB -1 -1 3.84 114924 3 4.76 -1 -1 71964 -1 -1 -1 115 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 854616 115 145 22865 19302 1 10319 1528 66 66 4356 DSP auto 177.7 MiB 240.81 312166 102042 872431 274471 588095 9865 776.7 MiB 10.52 0.10 5.768 4.76067 -21233.7 -4.76067 4.76067 0.03 0.0112499 0.00937755 1.28065 1.06586 -1 -1 -1 -1 -1 102221 14 2.52497e+08 9.57084e+07 8.29171e+07 19035.1 15.90 1.64146 1.36816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
7series_BRAM_DSP_carry.xml stereovision2.v common 1075.22 vpr 2.05 GiB -1 -1 5.50 172452 3 2.26 -1 -1 140992 -1 -1 -1 149 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2146896 149 182 55416 37075 1 33280 4031 106 106 11236 DSP auto 331.5 MiB 770.59 1.74668e+06 450674 3595535 1133232 2334220 128083 1925.1 MiB 87.23 0.75 22.9595 15.3724 -48322.5 -15.3724 15.3724 0.07 0.0319348 0.027826 3.8538 3.21492 -1 -1 -1 -1 -1 436136 16 6.67318e+08 2.79446e+08 2.17352e+08 19344.2 53.10 4.97283 4.15748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
7series_BRAM_DSP_carry.xml stereovision2.v common 1075.22 vpr 2.05 GiB -1 -1 5.50 172452 3 2.26 -1 -1 140992 -1 -1 -1 149 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 2146896 149 182 55416 37075 1 33280 4031 106 106 11236 DSP auto 331.5 MiB 770.59 1.74668e+06 450674 3595535 1133232 2334220 128083 1925.1 MiB 87.23 0.75 22.9595 15.3724 -48322.5 -15.3724 15.3724 0.07 0.0319348 0.027826 3.8538 3.21492 -1 -1 -1 -1 -1 436136 16 6.67318e+08 2.79446e+08 2.17352e+08 19344.2 53.10 4.97283 4.15748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
2 changes: 1 addition & 1 deletion ...ow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
7series_BRAM_DSP_carry.xml stereovision3.v common 2.53 vpr 72.59 MiB -1 -1 0.33 26408 4 0.08 -1 -1 36120 -1 -1 -1 11 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 74336 11 2 303 283 2 114 35 7 7 49 CLB auto 33.2 MiB 1.18 577.007 408 947 108 584 255 72.6 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000171885 0.000143559 0.00458104 0.00401289 -1 -1 -1 -1 40 889 22 1.34735e+06 1.18567e+06 152291. 3107.98 0.22 0.0179847 0.0160687 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.00962131 0.00895172
7series_BRAM_DSP_carry.xml diffeq2.v common 48.98 vpr 129.37 MiB -1 -1 0.19 27844 5 0.09 -1 -1 38944 -1 -1 -1 66 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 132476 66 96 1819 1080 1 1150 336 26 26 676 DSP auto 40.6 MiB 2.77 20198.7 9188 64521 14520 45607 4394 119.7 MiB 0.65 0.01 22.6842 19.668 -1065.49 -19.668 19.668 3.45 0.000811128 0.000723384 0.0536543 0.0478746 -1 -1 -1 -1 74 12093 17 3.53732e+07 1.31407e+07 5.36197e+06 7931.91 33.65 0.395666 0.356239 133518 2720184 -1 10986 14 5828 10018 3165525 816384 19.4143 19.4143 -1210.49 -19.4143 -1.7 -0.034 6.54552e+06 9682.72 1.89 0.38 1.55 -1 -1 1.89 0.0458825 0.0428936
7series_BRAM_DSP_carry.xml diffeq2.v common 48.98 vpr 129.37 MiB -1 -1 0.19 27844 5 0.09 -1 -1 38944 -1 -1 -1 66 0 -1 success v8.0.0-13067-gda604502c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.15.0-119-generic x86_64 2025-06-16T13:26:41 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks 132476 66 96 1819 1080 1 1150 336 26 26 676 DSP auto 40.6 MiB 2.77 20198.7 9188 64521 14520 45607 4394 119.7 MiB 0.65 0.01 22.6842 19.668 -1065.49 -19.668 19.668 3.45 0.000811128 0.000723384 0.0536543 0.0478746 -1 -1 -1 -1 74 12093 17 3.53732e+07 1.31407e+07 5.36197e+06 7931.91 33.65 0.395666 0.356239 133518 2720184 -1 10986 14 5828 10018 3165525 816384 19.4143 19.4143 -1210.49 -19.4143 -1.7 -0.034 6.54552e+06 9682.72 1.89 0.38 1.55 -1 -1 1.89 0.0458825 0.0428936
Loading
You are viewing a condensed version of this merge commit. You can view the full changes here.