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Merged
merged 102 commits into from
Jul 13, 2025
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b6371d2
[vpr][rr_graph] add tileable rr graph dir
amin1377 Jun 11, 2025
77781b4
[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation
amin1377 Jun 11, 2025
cf95e2c
[vpr][route] update rr_graph generation with tileable rr graph
amin1377 Jun 11, 2025
431923c
[vpr][util] add is_inter_cluster_node for vib arch
amin1377 Jun 11, 2025
d62fb79
[vpr][route] update router lookahead with tileable rr graph
amin1377 Jun 11, 2025
02a56e9
[vpr][blif] use regex to find param val
amin1377 Jun 11, 2025
204a794
[vpr][base] update with tileable rr graph
amin1377 Jun 11, 2025
7edf56d
[vpr][route] remove unused param
amin1377 Jun 11, 2025
f5e8061
[lib][arch] add vib processing
amin1377 Jun 11, 2025
14064c7
[lib][arch] add vib_inf
amin1377 Jun 11, 2025
49b04b0
[libs][rr_graph] update lib rr graph with tileable
amin1377 Jun 11, 2025
c6df91a
[libs][rr graph][io] update read/write rr graph functions with tileab…
amin1377 Jun 11, 2025
bf19150
[libs][rr graph][io] update rr_grpah utils with tileable info
amin1377 Jun 11, 2025
3970db7
[lib][rr_graph] add vtr tokenizer
amin1377 Jun 11, 2025
797b488
[lib][util] update capnp and util with open fpga
amin1377 Jun 11, 2025
cf2dbc8
add openfpga doc
amin1377 Jun 11, 2025
0e03dc7
[vpr][base] add vib grid
amin1377 Jun 11, 2025
f8fae78
add VIB doc
amin1377 Jun 11, 2025
5462ccd
[vpr][route] fix alloc_and_load_rr_switch_inf definition
amin1377 Jun 11, 2025
7cdf5bf
make format
amin1377 Jun 11, 2025
5ad8303
[vtr_flow][test] add openfpga arch
amin1377 Jun 11, 2025
c79ab8f
[CI] add openfpga tests
amin1377 Jun 11, 2025
8eccbcc
fix formatting
amin1377 Jun 11, 2025
0cc6f10
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 12, 2025
5a492c8
[doc][arch] add tileable doc
amin1377 Jun 12, 2025
1fd866e
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 16, 2025
5580c86
[libs][arch] add function declarations
amin1377 Jun 16, 2025
a27f6ba
[rr_graph] change MEDIUM node type name and related function to MUX
amin1377 Jun 16, 2025
8625ff0
[libs][arch] add process_bend
amin1377 Jun 16, 2025
57c1919
make format
amin1377 Jun 16, 2025
29c9677
[doc] fix a typo in .bib file
amin1377 Jun 16, 2025
b6fdda3
[vpr] remove redundant version of is_inter_cluster_node
amin1377 Jun 16, 2025
2b68252
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 18, 2025
65102b9
[doc][arch] move openfpga doc to the end of the file
amin1377 Jun 18, 2025
757e2f7
[doc][arch] add figures related to direct connection
amin1377 Jun 18, 2025
2b2fbb4
[doc][arch] add doc related to tileable direct interconnect
amin1377 Jun 18, 2025
6e5070c
[arch] change isbend to is_bend
amin1377 Jun 18, 2025
43ac8b4
[tileable_rr_graph] fix sub_fs formatting
amin1377 Jun 18, 2025
5436025
[rr_graph] comment tileable rr_graph function under rr_graph_builder.h
amin1377 Jun 18, 2025
09c90f2
[libs][rr_graph] mode bend_start/end out of t_rr_node_data
amin1377 Jun 18, 2025
e3df5b5
[base] fix function names formatting
amin1377 Jun 18, 2025
e08cd8c
make format
amin1377 Jun 18, 2025
9c87418
[libs][matrix] check for size before filling the matrix
amin1377 Jun 18, 2025
0df7730
[libs][rr_graph] fix node_bend_start/end size
amin1377 Jun 19, 2025
837278b
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 19, 2025
7c6a979
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 19, 2025
ca95008
[libs][arch] fix c-style code in read_xml_arch_file
amin1377 Jun 23, 2025
bb9a338
[lib][arch] fix process_vib_block_type_locs style
amin1377 Jun 23, 2025
af27706
[lib][arch] pass set funcitons params by reference
amin1377 Jun 23, 2025
4194e81
Apply code review comment
amin1377 Jun 23, 2025
561a0d5
make format
amin1377 Jun 23, 2025
07d4bac
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 24, 2025
4e38274
fix a typo
amin1377 Jun 24, 2025
f324567
[libs][arch] fix clang-17 warning
amin1377 Jun 24, 2025
1f929ea
[vpr][route][tileable] replace VTR_LOG to VTR_LOG_DEBUG & fix c-style…
amin1377 Jun 24, 2025
bc7ffcd
[libs][vtrutil] fix string_view error
amin1377 Jun 24, 2025
9cf3775
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 25, 2025
5f1939c
[vpr][utils] move StringToken under vtr util
amin1377 Jun 25, 2025
bd62d9f
[vpr][base] remove unnecessary auto
amin1377 Jun 25, 2025
1d1318d
[vpr] apply code format rules to tileable RR Graph files
amin1377 Jun 25, 2025
4c60c9d
[libs][arch] move vib arch functions to a separate file
amin1377 Jun 25, 2025
70836c5
make format
amin1377 Jun 25, 2025
2b101ef
[doc] fix grammatical issues
amin1377 Jun 28, 2025
edd3617
[libs][arch] fix sb_type sb_sub_type name
amin1377 Jun 28, 2025
205514f
[libs][arch] fix formatting
amin1377 Jun 28, 2025
28fc161
[libs][arch] fix code formatting
amin1377 Jun 29, 2025
59f1c86
[libs][arch] replace e_parallel_axis_vib with e_parallel_axis
amin1377 Jun 29, 2025
55c3f2f
[libs][rr_graph] fix tileable rr graph code format
amin1377 Jun 29, 2025
d168828
[libs][util] extern out_file_prefix
amin1377 Jun 29, 2025
34d0e65
[vpr][route] add e_parallel_axis identifier for all members
amin1377 Jun 30, 2025
7beed40
[libs][arch] add a method to parse tileable arch tags
amin1377 Jun 30, 2025
211c270
[libs][rr_graph] add comment for tileable rr graph
amin1377 Jun 30, 2025
4cc25a4
make format
amin1377 Jun 30, 2025
b38dbae
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jun 30, 2025
3e52cd6
[libs][arch] remove multiple definitons of e_directionality
amin1377 Jun 30, 2025
19452e9
[vpr][base] set type name to nullptr if type is null
amin1377 Jun 30, 2025
855abff
[lib][arch] fix clag warning by passing string as c_str
amin1377 Jun 30, 2025
ee1c9bd
[libs][arch] set fs value before calling process_tileable_device_para…
amin1377 Jun 30, 2025
586e56e
[libs] update submodules
amin1377 Jul 2, 2025
78c0583
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jul 2, 2025
326077b
[vpr][util] move find_tile_type_by_name impl under physcial_types_uti…
amin1377 Jul 2, 2025
4c66882
[vpr][route] move alloc_and_load_clb_to_clb_directs under clb2clb_dir…
amin1377 Jul 2, 2025
adec8f6
[vpr][route] fix formatting issues in tileable rr graph
amin1377 Jul 2, 2025
5c18569
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jul 2, 2025
abd0116
make format
amin1377 Jul 2, 2025
e03a84d
[vpr][tileable] move comments from cpp to .h + fix formatting
amin1377 Jul 8, 2025
556d499
[vpr][tileable] fix commenting style
amin1377 Jul 8, 2025
ec190c3
[vpr][tileable] remove const reference to ids
amin1377 Jul 8, 2025
78b4342
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jul 8, 2025
c6d641d
make format
amin1377 Jul 8, 2025
1486073
[libs][arch] move e_parallel_axis to logic_types
amin1377 Jul 8, 2025
0a6eb59
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jul 9, 2025
8c1729e
make format
amin1377 Jul 9, 2025
262ab69
[libs][rr_graph] add is_tileable to rr_graph_storage
amin1377 Jul 9, 2025
477103a
[route][rr_grpah] set is_tileable to true when building tileable rr g…
amin1377 Jul 9, 2025
5e24230
[vpr][base] add setup_vib_utils
amin1377 Jul 9, 2025
b6becb2
[vpr][base] create a new diretory for vib-specific grid
amin1377 Jul 9, 2025
1a7986a
update check_route for MUX type
amin1377 Jul 9, 2025
7544f77
[rr_graph] raise error if chanxy min loc is less than zero
amin1377 Jul 9, 2025
907565a
[libs][rr_graph] reserve capacity for node_bend_
amin1377 Jul 10, 2025
865b4bb
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Jul 10, 2025
530f53e
Merge branch 'master' into add_tileable_rr_graph
amin1377 Jul 13, 2025
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make format
  • Loading branch information
amin1377 committed Jul 9, 2025
commit 8c1729e6c9ebc7bffe807dbd75bc42df369347ab
2 changes: 1 addition & 1 deletion libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
Original file line number Diff line number Diff line change
Expand Up @@ -832,7 +832,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
seg_index_[rr_graph.node_cost_index(node.id())] = segment_id;
} else if (rr_graph.node_type(node.id()) == e_rr_type::CHANZ) {
// TODO: Don't use CHANX info
int seg_ind_z = find_segment_index_along_axis(segment_id, X_AXIS);
int seg_ind_z = find_segment_index_along_axis(segment_id, e_parallel_axis::X_AXIS);
rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(CHANX_COST_INDEX_START + seg_ind_z));
seg_index_[rr_graph.node_cost_index(node.id())] = segment_id;
}
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