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In debug mode, the STA checks if the incremental STA matches the STA computed from scratch. In this check it checked for if the critical nodes matched; however, the nodes returned are not stably deterministic (it does not break ties in a deterministic way). After discussing with Vaughn, it is safe to just remove the nodes check since it would not change the result of the analysis.

closes #2754

In debug mode, the STA checks if the incremental STA matches the STA
computed from scratch. In this check it checked for if the critical
nodes matched; however, the nodes returned are not stably deterministic
(it does not break ties in a deterministic way). After discussing with
Vaughn, it is safe to just remove the nodes check since it would not
change the result of the analysis.

closes verilog-to-routing#2754
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Oct 15, 2024
@AlexandreSinger
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@vaughnbetz This PR has passed CI. This fixed the STA issue we discussed.

@vaughnbetz vaughnbetz merged commit dc3e5dc into verilog-to-routing:master Oct 17, 2024
36 of 53 checks passed
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Thanks Alex!

@AlexandreSinger AlexandreSinger deleted the feature-incr-slack-issue branch November 27, 2024 19:23
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[Routing] Incremental Slack Timing Analysis Does Not Match When Computed From Scratch

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