Contains the code examples from The UVM Primer Book sorted by chapters.

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

VHDL compiler and simulator

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VeeR EL2 Core

A minimal GPU design in Verilog to learn how GPUs work from the ground up

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

VeeR EH1 core

BaseJump STL: A Standard Template Library for SystemVerilog

Common SystemVerilog components

Verilog digital signal processing components

Verilog UART

Verilog I2C interface for FPGA implementation

Verilog Ethernet components for FPGA implementation

Verilog PCI express components

Verilog AXI components for FPGA implementation

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Free, open source crypto trading bot

Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)

All Algorithms implemented in Java

This repository consists of the code samples, assignments, and notes for the Java data structures & algorithms + interview preparation bootcamp of WeMakeDevs.

Explain complex systems using visuals and simple terms. Help you prepare for system design interviews.

A list of back-end related questions you can be inspired from to interview potential candidates, test yourself or completely ignore

Master programming by recreating your favorite technologies from scratch.