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Fix uart initialization #30

Merged
merged 2 commits into from
Jun 10, 2021
Merged

Fix uart initialization #30

merged 2 commits into from
Jun 10, 2021

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andrejro
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@andrejro andrejro commented Jun 7, 2021

Fixes for 1. and 3. of issue #29

Andrej Rosano added 2 commits June 7, 2021 11:07
Static /6 divider is used for PLL3_FREQ derived clocks only.

#29
Check for tx FIFO to not be full instead of waiting to be empty after
every write.

#29
@andrejro andrejro mentioned this pull request Jun 7, 2021
@andrejro andrejro merged commit 47a6747 into master Jun 10, 2021
@andrejro andrejro deleted the fix-uart-initialization branch June 10, 2021 07:53
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