riscv: keep mstatus.MPP=M after mret on harts without U-mode

[carlosqwqqwq]

riscv: keep mstatus.MPP=M after mret on harts without U-mode

Fixes #2391

Problem

helper_mret always writes mstatus.MPP = PRV_U. On a hart whose MISA omits U, M is the least-privileged supported mode, so the post-mret MPP state must remain M.

Change

Update qemu/target/riscv/op_helper.c:helper_mret() to select PRV_U when RVU is present and PRV_M otherwise, matching the supported privilege modes of the hart.

Validation

• Rebased onto dev and built the RISC-V targets.
• The full test_riscv suite passes.
• A targeted public-API reproducer using a U-clear riscv_any configuration leaves the post-mret privilege state at M; the U-enabled control remains unchanged.
• The public CPU model list has no U-clear preset, so the U-clear case is documented as a manual API reproducer rather than adding a test-only CPU model.

[carlosqwqqwq]

Thank you very much for taking the time to review this PR. We have rebased it onto dev and updated the mret MPP handling for harts without U-mode, with focused validation of the affected behavior. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.