riscv: gate fsgnj.d/fmv.d on FPU and D extension

[carlosqwqqwq]

riscv: gate fsgnj.d/fmv.d on FPU and D extension

Fixes #2388

Problem

trans_fsgnj_d lacks the FPU and D-extension checks used by the other D-extension translators. Consequently, fsgnj.d and fmv.d can retire on the SiFive E51 model even though that model does not advertise F or D.

Change

Add REQUIRE_FPU; and REQUIRE_EXT(ctx, RVD); at the start of qemu/target/riscv/insn_trans/trans_rvd.inc.c:trans_fsgnj_d(), matching the neighboring D-extension translators.

Validation

• Rebased onto dev and built the RISC-V targets.
• Added an E51 regression case to tests/unit/test_riscv.c.
• Existing RV32 and RV64 floating-point move cases now set mstatus.FS=Dirty explicitly so they model an enabled floating-point state.
• The full test_riscv suite passes; D-enabled control execution remains successful.

[carlosqwqqwq]

Thank you very much for taking the time to review this PR. We have rebased it onto dev, added the required feature checks, and added focused coverage for an RV64 CPU without the D extension. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.