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Add hello world example based on code from minispartan6-audio.
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‎src_c/arch/riscv/assert.c‎

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extern void _exit(int rc);
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//-----------------------------------------------------------------
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// assert_handler:
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//-----------------------------------------------------------------
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void assert_handler(const char * type, const char *reason, const char *file, int line)
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{
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printf("%s: %s (%s:%d)\n", type, reason, file, line);
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_exit(-1);
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}

‎src_c/arch/riscv/assert.h‎

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#ifndef __ASSERT_H__
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#define __ASSERT_H__
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extern void assert_handler(const char * type, const char *reason, const char *file, int line);
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#define assert(exp) do { if (!(exp)) assert_handler("ASSERT", #exp, __FILE__, __LINE__ ); } while (0)
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#define panic(reason) do { assert_handler("PANIC", #reason, __FILE__, __LINE__ ); } while (0)
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#endif
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‎src_c/arch/riscv/boot.S‎

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.global init
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.global main
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.global irq_handler
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#####################################################
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# Entry point
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#####################################################
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.org 0x0
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boot_vector:
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j start
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#####################################################
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# IPC Vector
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#####################################################
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.org 0x8
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ipc_vector:
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.zero
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#####################################################
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# ISR Vector
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#####################################################
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.org 0x10
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j int_vector
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#####################################################
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# Arg handling
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#####################################################
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.org 0x20
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arg_argc:
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.space 4, 0
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arg_argv:
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.space 256, 0
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#####################################################
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# Actual ISR vector
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#####################################################
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int_vector:
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#include "exception_asm.h"
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#####################################################
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# Start
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#####################################################
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start:
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# Setup stack pointer
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lui sp, %hi(_sp)
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add sp, sp, %lo(_sp)
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# Setup IRQ vector
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lui t0, %hi(isr_vector)
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add t0, t0, %lo(isr_vector)
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csrw mtvec, t0
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# t0 = _bss_start
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lui t0,%hi(_bss_start)
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add t0,t0,%lo(_bss_start)
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# t1 = _end
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lui t1,%hi(_end)
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add t1,t1,%lo(_end)
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bss_clear:
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#ifndef SKIP_BSS_INIT
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sw x0, (0)(t0) # Write 0x00 to mem[t0]
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add t0, t0, 4 # t0 += 4
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blt t0, t1, bss_clear # Branch back to bss_clear if (t0 < t1)
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#endif
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# Jump to init
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jal init
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# Run main
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# a0 = argc
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la a0, arg_argc
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lw a0, 0(a0)
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# a1 = argv
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la a1, arg_argv
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jal main
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# Exit
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jal _exit
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#####################################################
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# Exit
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#####################################################
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.global _exit
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_exit:
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csrw dscratch, x0
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_exit_loop:
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jal _exit_loop

‎src_c/arch/riscv/csr.h‎

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#ifndef __CSR_H__
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#define __CSR_H__
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#include <stdint.h>
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//-----------------------------------------------------------------
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// Defines:
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//-----------------------------------------------------------------
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#define SR_SIE (1 << 1)
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#define SR_MIE (1 << 3)
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#define SR_SPIE (1 << 5)
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#define SR_MPIE (1 << 7)
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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#define SR_IP_MSIP (1 << IRQ_M_SOFT)
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#define SR_IP_MTIP (1 << IRQ_M_TIMER)
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#define SR_IP_MEIP (1 << IRQ_M_EXT)
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#define SR_IP_SSIP (1 << IRQ_S_SOFT)
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#define SR_IP_STIP (1 << IRQ_S_TIMER)
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#define SR_IP_SEIP (1 << IRQ_S_EXT)
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//-----------------------------------------------------------------
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// Helpers:
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//-----------------------------------------------------------------
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#define csr_read(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define csr_write(reg, val) ({ \
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asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
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#define csr_set(reg, bit) ({ unsigned long __tmp; \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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__tmp; })
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#define csr_clear(reg, bit) ({ unsigned long __tmp; \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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__tmp; })
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#define csr_swap(reg, val) ({ \
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unsigned long __v = (unsigned long)(val); \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
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__v; })
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//-----------------------------------------------------------------
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// csr_set_isr_vector: Set exception vector
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//-----------------------------------------------------------------
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static inline void csr_set_isr_vector(uint32_t addr)
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{
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asm volatile ("csrw mtvec, %0": : "r" (addr));
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}
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//-----------------------------------------------------------------
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// csr_get_time: Get current time (MTIME)
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//-----------------------------------------------------------------
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static inline uint32_t csr_get_time(void)
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{
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uint32_t value;
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asm volatile ("csrr %0, time" : "=r" (value) : );
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return value;
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}
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//-----------------------------------------------------------------
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// csr_set_time_compare: Set value to generate timer IRQ at
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//-----------------------------------------------------------------
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static inline void csr_set_time_compare(uint32_t value)
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{
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// Value 0 is ignored...
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if (value == 0) value = 1;
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asm volatile ("csrw time, %0": : "r" (value));
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}
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//-----------------------------------------------------------------
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// csr_set_irq_mask: Enable particular interrupts
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//-----------------------------------------------------------------
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static inline void csr_set_irq_mask(uint32_t mask)
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{
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asm volatile ("csrs mie,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_clr_irq_mask: Disable particular interrupts
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//-----------------------------------------------------------------
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static inline void csr_clr_irq_mask(uint32_t mask)
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{
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asm volatile ("csrc mie,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_get_irq_pending: Bitmap of pending IRQs
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//-----------------------------------------------------------------
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static inline uint32_t csr_get_irq_pending(void)
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{
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uint32_t value;
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asm volatile ("csrr %0, mip" : "=r" (value) : );
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return value;
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}
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//-----------------------------------------------------------------
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// csr_set_irq_pending: Set pending interrupts (SW IRQ)
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//-----------------------------------------------------------------
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static inline void csr_set_irq_pending(uint32_t mask)
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{
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asm volatile ("csrs mip,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_irq_ack: Clear pending interrupts
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//-----------------------------------------------------------------
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static inline void csr_irq_ack(uint32_t mask)
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{
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asm volatile ("csrc mip,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_set_irq_enable: Global IRQ enable
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//-----------------------------------------------------------------
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static inline void csr_set_irq_enable(void)
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{
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uint32_t mask = SR_MIE;
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asm volatile ("csrs mstatus,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_clr_irq_enable: Gloabl IRQ disable
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//-----------------------------------------------------------------
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static inline void csr_clr_irq_enable(void)
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{
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uint32_t mask = SR_MIE;
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asm volatile ("csrc mstatus,%0": : "r" (mask));
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}
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//-----------------------------------------------------------------
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// csr_get_irq_enable: Get current IRQ enable state
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//-----------------------------------------------------------------
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static inline int csr_get_irq_enable(void)
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{
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uint32_t value;
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uint32_t mask = SR_MIE;
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asm volatile ("csrr %0, mstatus" : "=r" (value) : );
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return (value & mask) != 0;
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}
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#endif

‎src_c/arch/riscv/exception.c‎

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#include "exception.h"
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#include "assert.h"
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#include "csr.h"
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//-----------------------------------------------------------------
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// Defines:
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//-----------------------------------------------------------------
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#define SR_MPP_SHIFT 11
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#define SR_MPP_MASK 0x3
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#define SR_MPP (SR_MPP_MASK << SR_MPP_SHIFT)
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#define SR_MPP_M (3 << SR_MPP_SHIFT)
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//-----------------------------------------------------------------
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// Locals
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//-----------------------------------------------------------------
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#define CAUSE_MAX_EXC (CAUSE_PAGE_FAULT_STORE + 1)
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static fp_exception _exception_table[CAUSE_MAX_EXC];
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static fp_irq _irq_handler = 0;
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void exception_set_irq_handler(fp_irq handler) { _irq_handler = handler; }
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void exception_set_syscall_handler(fp_syscall handler)
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{
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_exception_table[CAUSE_ECALL_U] = handler;
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_exception_table[CAUSE_ECALL_S] = handler;
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_exception_table[CAUSE_ECALL_M] = handler;
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}
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void exception_set_handler(int cause, fp_exception handler)
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{
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_exception_table[cause] = handler;
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}
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//-----------------------------------------------------------------
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// exception_handler:
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//-----------------------------------------------------------------
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struct irq_context * exception_handler(struct irq_context *ctx)
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{
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#ifndef EXCEPTION_SP_FROM_MSCRATCH
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// Fix-up MPP so that we stay in machine mode
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ctx->status &= ~SR_MPP;
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ctx->status |= SR_MPP_M;
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#endif
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// External interrupt
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if (ctx->cause & CAUSE_INTERRUPT)
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{
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if (_irq_handler)
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ctx = _irq_handler(ctx);
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else
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printf("Unhandled IRQ!\n");
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}
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// Exception
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else
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{
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switch (ctx->cause)
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{
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case CAUSE_ECALL_U:
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case CAUSE_ECALL_S:
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case CAUSE_ECALL_M:
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ctx->pc += 4;
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break;
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}
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if (ctx->cause < CAUSE_MAX_EXC && _exception_table[ctx->cause])
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ctx = _exception_table[ctx->cause](ctx);
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else
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{
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printf("Unhandled exception: PC 0x%08x Cause %d!\n", ctx->pc, ctx->cause);
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assert(!"Unhandled exception");
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}
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}
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return ctx;
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}

‎src_c/arch/riscv/exception.h‎

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#ifndef __EXCEPTION_H__
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#define __EXCEPTION_H__
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#include <stdint.h>
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#include "csr.h"
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//-----------------------------------------------------------------
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// Defines:
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//-----------------------------------------------------------------
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#define REG_RA 1
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#define REG_SP 2
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#define REG_ARG0 10
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#define REG_RET REG_ARG0
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#define NUM_GP_REG 32
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#define NUM_CSR_REG 3
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#define CAUSE_MISALIGNED_FETCH 0
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#define CAUSE_FAULT_FETCH 1
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#define CAUSE_ILLEGAL_INSTRUCTION 2
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#define CAUSE_BREAKPOINT 3
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#define CAUSE_MISALIGNED_LOAD 4
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#define CAUSE_FAULT_LOAD 5
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#define CAUSE_MISALIGNED_STORE 6
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#define CAUSE_FAULT_STORE 7
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#define CAUSE_ECALL_U 8
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#define CAUSE_ECALL_S 9
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#define CAUSE_ECALL_M 11
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#define CAUSE_PAGE_FAULT_INST 12
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#define CAUSE_PAGE_FAULT_LOAD 13
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#define CAUSE_PAGE_FAULT_STORE 15
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#define CAUSE_INTERRUPT (1 << 31)
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//-----------------------------------------------------------------
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// Types:
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//-----------------------------------------------------------------
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struct irq_context
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{
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uint32_t pc;
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uint32_t status;
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uint32_t cause;
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uint32_t reg[NUM_GP_REG];
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};
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typedef struct irq_context *(*fp_exception)(struct irq_context *ctx);
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typedef struct irq_context *(*fp_irq)(struct irq_context *ctx);
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typedef struct irq_context *(*fp_syscall)(struct irq_context *ctx);
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//-----------------------------------------------------------------
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// context_irq_enable: Set future interrupt enable
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//-----------------------------------------------------------------
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static void context_irq_enable(struct irq_context *ctx, int enable)
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{
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// MPIE becomes MIE on return from exception
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ctx->status &= ~SR_MPIE;
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ctx->status |= (enable ? SR_MPIE : 0);
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}
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//-----------------------------------------------------------------
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// Prototypes:
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//-----------------------------------------------------------------
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struct irq_context * exception_handler(struct irq_context *ctx);
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void exception_set_irq_handler(fp_irq irq_handler);
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void exception_set_syscall_handler(fp_syscall syscall_handler);
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void exception_set_handler(int cause, fp_exception handler);
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#endif
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