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skiphansenskiphansen
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Added panologic-g2 target.
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‎fpga/panologic_g2/.gitignore‎

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project

‎fpga/panologic_g2/Makefile‎

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###############################################################################
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## Makefile
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###############################################################################
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CPU ?= riscv
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XILINX_ISE ?= /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
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CABLE ?= jtaghs2
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# Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
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RISCV_CORE ?= rv32i_spartan6
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PART_NAME = xc6slx150
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PART_PACKAGE = fgg484
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PART_SPEED = 2
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SRC_DIR = .
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SRC_DIR += ../common
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SRC_DIR += ../../soc/core_soc/src_v
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SRC_DIR += ../../soc/dbg_bridge/src_v
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CORES_README = ../../soc/core_soc/README.md
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# RISC-V
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ifeq ($(CPU),riscv)
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SRC_DIR += ../../cpu/riscv/core/$(RISCV_CORE)
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SRC_DIR += ../../cpu/riscv/top_tcm_wrapper
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EXTRA_VFLAGS += CPU_SELECT_RISCV=1
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else
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# Cortex M0
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SRC_DIR += ../../cpu/cortex_m0/src_v
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EXTRA_VFLAGS += CPU_SELECT_ARMV6M=1
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endif
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.PHONY: init_and_build
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init_and_build: ${CORES_README} all
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include ../common/makefile.fpga_ise
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load:
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xc3sprog -c ${CABLE} project/${PROJECT}_routed.bit
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${CORES_README}:
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git submodule init
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git submodule update
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‎fpga/panologic_g2/README.md‎

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## Target: Second generation Panologic thin client
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![](./assets/pano.png)
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If you don't know what a Panologic thin client then see [this](https://hackaday.com/2013/01/11/ask-hackaday-we-might-have-some-fpgas-to-hack/)
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article and refer to the links at the bottom of this page for further reading.
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### HW Requirements
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* A Panologic G2 thin client (the one with a DVI port)
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* A suitable 5 volt power supply
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* A JTAG programmer to load the bitstream into the FPGA.
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### Building from sources
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**NB:** While it may be possible to use Windows for development I haven't
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tried it and don't recommend it.
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1. Clone the https://github.com/skiphansen/fpga_test_soc repository
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2. cd into .../fpga_test_soc/fpga/panologic_g2
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3. If you have a **REV B** Pano with the larger FPGA then just run "make",
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otherwise if you have a **REV C** then run "make PART_NAME=xc6slx100".
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### Serial port
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We will use the DDC port on the micro HDMI port for our serial port. This
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will leave the DVI port available for a display if needed.
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| HDMI Signal | Pin | Serial signal |
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| ----------- | ----- | ------------- |
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| DDC SCL | 15 | PC -> Pano |
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| DDC SDA | 16 | Pano -> PC |
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| Ground | 17 | Ground |
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An 3.3 volt compatible serial port adapter and an homebrew adapter cable is
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required.
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I use a FTDI [TTL-232R-3V3](https://www.digikey.com/product-detail/en/ftdi-future-technology-devices-international-ltd/TTL-232R-3V3/768-1015-ND/1836393)
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with an adapter that I built from a micro HDMI to HDMI adapter cable.
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![](./assets/micro_hdmi_adapter.png)
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To build the adapter I cut the micro to mini adapter cable, stripped the wires,
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identified the correct wires and then soldered them to .1 inch pin header to
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mate with my serial adapter. While I was eventually able to get the cable to
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work I **DO NOT RECOMMEND** following my lead. The wires in the adapter cable
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are VERY tiny and were very difficult to work with.
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If I were to do again I would use a micro HDMI to HDMI cable and a HDMI breakout
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board. This would be much easier to wire and would be more robust physically
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than the approach I took.
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![](./assets/micro_hdmi_cable.png)
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![](./assets/hdmi_adapter.png)
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[Adafruit](https://www.adafruit.com/product/3121) has an inexpensive breakout
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board that looks like it would be perfect.
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### Status
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The bit file build and the hello world program can be run, however the output
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doesn't match the expected output. I'm in the process of investigating the
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problem.
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### Pano Links
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- [Gitter](https://gitter.im/panologic/community) chat room for Panologic hackers.
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- Group.io [group](https://groups.io/g/panohackers/topics) for discussions about Panologic hacking
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- [Original Hackaday](https://hackaday.com/2013/01/11/ask-hackaday-we-might-have-some-fpgas-to-hack/) article from 2013.
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- Hackaday article on Tom's [Raytracker](https://hackaday.com/2018/12/07/racing-the-beam-on-a-thin-client-in-fpgas/).
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- Hackaday article on my [Pacman](https://hackaday.com/2019/01/11/pac-man-fever-comes-to-the-pano-logic-fpga/) project.
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- Hackaday article on Tom's [Joystick adapter](https://hackaday.com/2019/02/11/two-joysticks-talk-to-fpga-arcade-game-over-a-vga-cable/).
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- Wenting Zhang's [VerilogBoy](https://github.com/zephray/VerilogBoy) project.
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- Hackaday article on My [pano_progfpga](https://hackaday.com/2019/04/19/pano-logic-fgpa-hacking-just-got-easier/) project
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- My [prog_fpga](https://github.com/skiphansen/pano_progfpga) project.
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- My [pacman](https://github.com/skiphansen/pano_man) project.
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- My [Hello World](https://github.com/skiphansen/pano_hello_g1) project.
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- My [USB sniffer](https://github.com/skiphansen/usb_sniffer/blob/master/fpga/panologic_g2/README.md) project.
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- https://github.com/tomverbeure/panologic
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- G1 [Schematics!](https://github.com/twj42/PanoLogicG2_ReverseEngineering/blob/master/files/G1_Schematics.zip)
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- https://github.com/tomverbeure/panologic-g2
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- https://twj42.github.io/PanoLogicG2_ReverseEngineering/
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‎fpga/panologic_g2/assets/hdmi_adapter.png‎

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‎fpga/panologic_g2/assets/micro_hdmi_adapter.png‎

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‎fpga/panologic_g2/assets/micro_hdmi_cable.png‎

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‎fpga/panologic_g2/assets/pano.png‎

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‎fpga/panologic_g2/fpga.ucf‎

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# Clocks
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NET "SYSCLK" PERIOD = 125 MHz HIGH 50% | LOC = "Y13";
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# Flash
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NET "flash_cs_o" LOC="T5" | IOSTANDARD=LVCMOS33;
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NET "flash_sck_o" LOC="Y21" | IOSTANDARD=LVCMOS33;
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NET "flash_si_o" LOC="AB20" | IOSTANDARD=LVCMOS33;
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NET "flash_so_i" LOC="AA20" | IOSTANDARD=LVCMOS33;
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# serial cable connected to mini HDMI DDC signals
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NET "uart_txd_i" LOC="AA21" | IOSTANDARD=LVTTL; # AKA DDC2_SCK
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NET "uart_rxd_o" LOC="AB19" | IOSTANDARD=LVTTL; # AKA DDC2_SDA
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############################################################################
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# ULPI Interface
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############################################################################
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# ignore relative timing between the 60MHz USB reference clock and the processing clock CLK_P
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#NET "u_pll/CLKOUT0" TNM_NET = TNM_NET_USB_CLK60G;
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#NET "USB_CLK60G" TNM_NET = "TNM_NET_USB_CLK60G"; # all synchronous elements after BUFG
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#TIMESPEC "TS_USB_CLK60G" = PERIOD "TNM_NET_USB_CLK60G" 16.666 ns HIGH 50%;
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#NET "USB_ULPI_DATA<0>" LOC = "A7" ;
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#NET "USB_ULPI_DATA<1>" LOC = "B8" ;
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#NET "USB_ULPI_DATA<2>" LOC = "A8" ;
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#NET "USB_ULPI_DATA<3>" LOC = "D6" ;
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#NET "USB_ULPI_DATA<4>" LOC = "C6" ;
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#NET "USB_ULPI_DATA<5>" LOC = "B6" ;
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#NET "USB_ULPI_DATA<6>" LOC = "A6" ;
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#NET "USB_ULPI_DATA<7>" LOC = "A4" ;
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#NET "USB_ULPI_STP" LOC = "A5" ;
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#NET "USB_ULPI_NXT" LOC = "C5" ;
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#NET "USB_ULPI_DIR" LOC = "C7" ;
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#NET "USB_CLK60" LOC = "C12" ;
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#INST "USB_ULPI_DATA<0>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<1>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<2>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<3>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<4>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<5>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<6>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_DATA<7>" TNM = USB_ULPI_OUT;
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#INST "USB_ULPI_STP" TNM = USB_ULPI_OUT;
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#TIMEGRP "USB_ULPI_OUT" OFFSET = OUT 8.5 ns AFTER USB_CLK60;
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#INST "USB_ULPI_DATA<0>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<1>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<2>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<3>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<4>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<5>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<6>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DATA<7>" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_NXT" TNM = USB_ULPI_IN;
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#INST "USB_ULPI_DIR" TNM = USB_ULPI_IN;
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#TIMEGRP "USB_ULPI_IN" OFFSET = IN 13.666 ns BEFORE USB_CLK60; #3ns at ULPI PHY output, period 16.6ns
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#NET "USB_ULPI_DATA<*>" IOSTANDARD = LVCMOS33;
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#NET "USB_ULPI_STP" IOSTANDARD = LVCMOS33;
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#NET "USB_ULPI_NXT" IOSTANDARD = LVCMOS33;
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#NET "USB_ULPI_DIR" IOSTANDARD = LVCMOS33;
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#NET "USB_CLK60" IOSTANDARD = LVCMOS33;
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# 24 Mhz USB3300 clock
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#NET "usb_clk" LOC = W12 | IOSTANDARD = LVCMOS33;
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# Ethernet PHY
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NET "GMII_RST_N" LOC = R11 | IOSTANDARD = LVCMOS33;
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#NET "led_red" LOC = E12 | IOSTANDARD = LVCMOS33;
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NET "led_blue" LOC = H13 | IOSTANDARD = LVCMOS33;
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#NET "led_green" LOC = F13 | IOSTANDARD = LVCMOS33;
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