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Porting the design to an AU50

Status: Open.

#9 In ucsdsysnet/Rosebud;

· slahmer97 opened on Apr 1, 2025

Cell is placed inside reconfig block

Status: Open.

#7 In ucsdsysnet/Rosebud;

· hoangvm97 opened on Mar 1, 2023

Compile with normal flow (no partial reconfig) error

Status: Open.

#6 In ucsdsysnet/Rosebud;

· hoangvm97 opened on Mar 1, 2023

Add RPU and interface count readbacks to the FPGA image

enhancementNew feature or requestNew feature or request

Status: Open.

#5 In ucsdsysnet/Rosebud;

· mkhazraee opened on Feb 11, 2023

Update PCIe modules to support straddling

enhancementNew feature or requestNew feature or request

Status: Open.

#4 In ucsdsysnet/Rosebud;

· mkhazraee opened on Nov 23, 2022

Testbenches insert packets at higher rate than 100Gbps per interface

enhancementNew feature or requestNew feature or request

Status: Open.

#3 In ucsdsysnet/Rosebud;

· mkhazraee opened on Nov 15, 2022

Very rarely a slot is returned to the LB which was supposed to be in LB and not the RPUs.

bugSomething isn't workingSomething isn't working

enhancementNew feature or requestNew feature or request

Status: Open.

#2 In ucsdsysnet/Rosebud;

· mkhazraee opened on Nov 15, 2022

Adjust when to drop packets per incoming interface for the RR scheduler

bugSomething isn't workingSomething isn't working

enhancementNew feature or requestNew feature or request

Status: Open.

#1 In ucsdsysnet/Rosebud;

· mkhazraee opened on Nov 15, 2022