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Refactor: Adjust bootrom reset vector address #196

Merged
merged 9 commits into from
Nov 2, 2023
Merged

Refactor: Adjust bootrom reset vector address #196

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49e5940
FIX: change bootrom
T-K-233 Apr 22, 2023
1ca8353
Merge branch 'master' of https://github.com/ucb-bar/testchipip into s…
T-K-233 May 21, 2023
f6a5f5a
Merge branch 'master' of https://github.com/ucb-bar/testchipip into s…
T-K-233 Jun 17, 2023
476fd8e
FIX: fix bootaddrreg location
T-K-233 Jun 17, 2023
6df18b2
Merge commit 'c80ec1cd799cd1d004dad1c381f3e7eac3ebdbcd' of https://gi…
T-K-233 Sep 3, 2023
4be9e32
Merge branch 'master' of https://github.com/ucb-bar/testchipip into HEAD
T-K-233 Sep 5, 2023
307fca3
FIX: change PC reset vector in cosim
T-K-233 Sep 26, 2023
e3fa307
FIX: make BOOT_ADDR_BASE a macro definition
T-K-233 Nov 1, 2023
c4c0774
Merge remote-tracking branch 'origin/master' into change-bootrom
jerryz123 Nov 2, 2023
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2 changes: 1 addition & 1 deletion src/main/resources/testchipip/bootrom/bootrom.S
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#define BOOTADDR_REG 0x4000
#define BOOTADDR_REG 0x1000
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// boot all cores (only hart 0) and jump to main program execution
.section .text.start, "ax", @progbits
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63 changes: 63 additions & 0 deletions src/main/resources/testchipip/bootrom/bootrom.rv32.dump
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Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@

bootrom.rv32.elf: file format elf32-littleriscv


Disassembly of section .text.hang:

00010000 <_hang>:
10000: 00000517 auipc a0,0x0
10004: 04050513 addi a0,a0,64 # 10040 <_start>
10008: 30551073 csrw mtvec,a0
1000c: 301022f3 csrr t0,misa
10010: 4122d293 srai t0,t0,0x12
10014: 0012f293 andi t0,t0,1
10018: 00028463 beqz t0,10020 <_hang+0x20>
1001c: 30301073 csrw mideleg,zero
10020: 00800513 li a0,8
10024: 30451073 csrw mie,a0
10028: 30052073 csrs mstatus,a0

0001002c <wfi_loop>:
1002c: 10500073 wfi
10030: ffdff06f j 1002c <wfi_loop>

Disassembly of section .text.start:

00010040 <_start>:
10040: 020005b7 lui a1,0x2000
10044: f1402573 csrr a0,mhartid
10048: 00050463 beqz a0,10050 <_start+0x10>
1004c: 0380006f j 10084 <boot_core>
10050: 00458613 addi a2,a1,4 # 2000004 <_dtb+0x1feff44>
10054: 00100693 li a3,1

00010058 <interrupt_loop>:
10058: 00d62023 sw a3,0(a2)
1005c: 00460613 addi a2,a2,4
10060: ffc62683 lw a3,-4(a2)
10064: fe069ae3 bnez a3,10058 <interrupt_loop>
10068: 02c0006f j 10094 <boot_core_hart0>

Disassembly of section .text.hang80:

00010080 <_hang80>:
10080: f81ff06f j 10000 <ROM_BASE>

00010084 <boot_core>:
10084: 0005a283 lw t0,0(a1)
10088: fe029ee3 bnez t0,10084 <boot_core>
1008c: 00251513 slli a0,a0,0x2
10090: 00b505b3 add a1,a0,a1

00010094 <boot_core_hart0>:
10094: 0005a023 sw zero,0(a1)
10098: 00001537 lui a0,0x1
1009c: 00052503 lw a0,0(a0) # 1000 <ROM_BASE-0xf000>
100a0: 34151073 csrw mepc,a0
100a4: f1402573 csrr a0,mhartid
100a8: 00000597 auipc a1,0x0
100ac: 01858593 addi a1,a1,24 # 100c0 <_dtb>
100b0: 08000613 li a2,128
100b4: 30063073 csrc mstatus,a2
100b8: 30200073 mret
100bc: 00000013 nop
Binary file modified src/main/resources/testchipip/bootrom/bootrom.rv32.img
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63 changes: 63 additions & 0 deletions src/main/resources/testchipip/bootrom/bootrom.rv64.dump
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Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@

bootrom.rv64.elf: file format elf64-littleriscv


Disassembly of section .text.hang:

0000000000010000 <_hang>:
10000: 00000517 auipc a0,0x0
10004: 04050513 addi a0,a0,64 # 10040 <_start>
10008: 30551073 csrw mtvec,a0
1000c: 301022f3 csrr t0,misa
10010: 4122d293 srai t0,t0,0x12
10014: 0012f293 andi t0,t0,1
10018: 00028463 beqz t0,10020 <_hang+0x20>
1001c: 30301073 csrw mideleg,zero
10020: 00800513 li a0,8
10024: 30451073 csrw mie,a0
10028: 30052073 csrs mstatus,a0

000000000001002c <wfi_loop>:
1002c: 10500073 wfi
10030: ffdff06f j 1002c <wfi_loop>

Disassembly of section .text.start:

0000000000010040 <_start>:
10040: 020005b7 lui a1,0x2000
10044: f1402573 csrr a0,mhartid
10048: 00050463 beqz a0,10050 <_start+0x10>
1004c: 0380006f j 10084 <boot_core>
10050: 00458613 addi a2,a1,4 # 2000004 <_dtb+0x1feff44>
10054: 00100693 li a3,1

0000000000010058 <interrupt_loop>:
10058: 00d62023 sw a3,0(a2)
1005c: 00460613 addi a2,a2,4
10060: ffc62683 lw a3,-4(a2)
10064: fe069ae3 bnez a3,10058 <interrupt_loop>
10068: 02c0006f j 10094 <boot_core_hart0>

Disassembly of section .text.hang80:

0000000000010080 <_hang80>:
10080: f81ff06f j 10000 <ROM_BASE>

0000000000010084 <boot_core>:
10084: 0005a283 lw t0,0(a1)
10088: fe029ee3 bnez t0,10084 <boot_core>
1008c: 00251513 slli a0,a0,0x2
10090: 00b505b3 add a1,a0,a1

0000000000010094 <boot_core_hart0>:
10094: 0005a023 sw zero,0(a1)
10098: 00001537 lui a0,0x1
1009c: 00053503 ld a0,0(a0) # 1000 <ROM_BASE-0xf000>
100a0: 34151073 csrw mepc,a0
100a4: f1402573 csrr a0,mhartid
100a8: 00000597 auipc a1,0x0
100ac: 01858593 addi a1,a1,24 # 100c0 <_dtb>
100b0: 08000613 li a2,128
100b4: 30063073 csrc mstatus,a2
100b8: 30200073 mret
100bc: 00000013 nop
Binary file modified src/main/resources/testchipip/bootrom/bootrom.rv64.img
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4 changes: 2 additions & 2 deletions src/main/resources/testchipip/bootrom/linker.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,9 @@ SECTIONS
ROM_BASE = 0x10000; /* ... but actually position independent */

. = ROM_BASE;
.text.start : { *(.text.start) }
. = ROM_BASE + 0x40;
.text.hang : { *(.text.hang) }
. = ROM_BASE + 0x40;
.text.start : { *(.text.start) }
. = ROM_BASE + 0x80;
.text.hang80 : { *(.text.hang80) }
}
2 changes: 1 addition & 1 deletion src/main/scala/BootAddrReg.scala
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Expand Up @@ -15,7 +15,7 @@ import freechips.rocketchip.prci._

case class BootAddrRegParams(
defaultBootAddress: BigInt = 0x80000000L, // This should be DRAM_BASE
bootRegAddress: BigInt = 0x4000,
bootRegAddress: BigInt = 0x1000,
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slaveWhere: TLBusWrapperLocation = PBUS
)
case object BootAddrRegKey extends Field[Option[BootAddrRegParams]](None)
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