Merge pull request #173 from ucb-bar/optionals

Make BootAddrReg an optionally-enabled feature
ucb-bar · May 10, 2023 · ebf6156 · ebf6156
2 parents 4b972de + cf1157e
commit ebf6156
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Showing 3 changed files with 30 additions and 14 deletions.
diff --git a/src/main/scala/BootAddrReg.scala b/src/main/scala/BootAddrReg.scala
@@ -18,21 +18,20 @@ case class BootAddrRegParams(
   bootRegAddress: BigInt = 0x4000,
   slaveWhere: TLBusWrapperLocation = PBUS
 )
-case object BootAddrRegKey extends Field[BootAddrRegParams](BootAddrRegParams())
+case object BootAddrRegKey extends Field[Option[BootAddrRegParams]](None)
 
-trait HasPeripheryBootAddrReg { this: BaseSubsystem =>
-  val params = p(BootAddrRegKey)
+trait CanHavePeripheryBootAddrReg { this: BaseSubsystem =>
+  p(BootAddrRegKey).map { params =>
+    val tlbus = locateTLBusWrapper(params.slaveWhere)
+    val device = new SimpleDevice("boot-address-reg", Nil)
 
-  val tlbus = locateTLBusWrapper(params.slaveWhere)
-
-  val device = new SimpleDevice("boot-address-reg", Nil)
-
-  tlbus {
-    val node = TLRegisterNode(Seq(AddressSet(params.bootRegAddress, 4096-1)), device, "reg/control", beatBytes=tlbus.beatBytes)
-    tlbus.toVariableWidthSlave(Some("boot-address-reg")) { node }
-    InModuleBody {
-      val bootAddrReg = RegInit(params.defaultBootAddress.U(p(XLen).W))
-      node.regmap(0 -> RegField.bytes(bootAddrReg))
+    tlbus {
+      val node = TLRegisterNode(Seq(AddressSet(params.bootRegAddress, 4096-1)), device, "reg/control", beatBytes=tlbus.beatBytes)
+      tlbus.toVariableWidthSlave(Some("boot-address-reg")) { node }
+      InModuleBody {
+        val bootAddrReg = RegInit(params.defaultBootAddress.U(p(XLen).W))
+        node.regmap(0 -> RegField.bytes(bootAddrReg))
+      }
     }
   }
 }
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
@@ -117,3 +117,19 @@ class WithTilesStartInReset(harts: Int*) extends Config((site, here, up) => {
 class WithNoSerialTL extends Config((site, here, up) => {
   case SerialTLKey => None
 })
+
+class WithBootAddrReg(params: BootAddrRegParams = BootAddrRegParams()) extends Config((site, here, up) => {
+  case BootAddrRegKey => Some(params)
+})
+
+class WithNoBootAddrReg extends Config((site, here, up) => {
+  case BootAddrRegKey => None
+})
+
+class WithCustomBootPin(params: CustomBootPinParams = CustomBootPinParams()) extends Config((site, here, up) => {
+  case CustomBootPinKey => Some(params)
+})
+
+class WithNoCustomBootPin extends Config((site, here, up) => {
+  case CustomBootPinKey => None
+})
diff --git a/src/main/scala/CustomBootPin.scala b/src/main/scala/CustomBootPin.scala
@@ -26,6 +26,7 @@ class WithCustomBootPinAltAddr(address: BigInt) extends Config((site, here, up)
 
 trait CanHavePeripheryCustomBootPin { this: BaseSubsystem =>
   val custom_boot_pin = p(CustomBootPinKey).map { params =>
+    require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg")
     val tlbus = locateTLBusWrapper(params.masterWhere)
     val clientParams = TLMasterPortParameters.v1(
       clients = Seq(TLMasterParameters.v1(
@@ -52,7 +53,7 @@ trait CanHavePeripheryCustomBootPin { this: BaseSubsystem =>
           is (waiting_bootaddr_reg_a) {
             tl.a.valid := true.B
             tl.a.bits := edge.Put(
-              toAddress = p(BootAddrRegKey).bootRegAddress.U,
+              toAddress = p(BootAddrRegKey).get.bootRegAddress.U,
               fromSource = 0.U,
               lgSize = 2.U,
               data = params.customBootAddress.U