Rename serialManagerParams -> serialTLManagerParams

ucb-bar · May 14, 2023 · 2e09aea · 2e09aea
1 parent 862a5db
commit 2e09aea
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Showing 3 changed files with 15 additions and 15 deletions.
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
@@ -68,7 +68,7 @@ class WithSerialTLWidth(width: Int) extends Config((site, here, up) => {
 })
 
 class WithAXIMemOverSerialTL(axiMemOverSerialTLParams: AXIMemOverSerialTLClockParams) extends Config((site, here, up) => {
-  case SerialTLKey => up(SerialTLKey).map(s => s.copy(serialManagerParams=s.serialManagerParams.map(
+  case SerialTLKey => up(SerialTLKey).map(s => s.copy(serialTLManagerParams=s.serialTLManagerParams.map(
     _.copy(axiMemOverSerialTLParams=Some(axiMemOverSerialTLParams)))))
 })
 
@@ -102,7 +102,7 @@ class WithSerialTLMem(
       beatBytes = site(MemoryBusKey).beatBytes
     )
     up(SerialTLKey, site).map { k => k.copy(
-      serialManagerParams = Some(k.serialManagerParams.getOrElse(SerialTLManagerParams(memParams = masterPortParams))
+      serialTLManagerParams = Some(k.serialTLManagerParams.getOrElse(SerialTLManagerParams(memParams = masterPortParams))
         .copy(memParams = masterPortParams, isMemoryDevice = isMainMemory)
       )
     )}
@@ -113,22 +113,22 @@ class WithSerialTLMem(
 class WithSerialTLBackingMemory extends Config((site, here, up) => {
   case ExtMem => None
   case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
-    serialManagerParams = Some(k.serialManagerParams.getOrElse(SerialTLManagerParams(memParams = up(ExtMem).get.master))
+    serialTLManagerParams = Some(k.serialTLManagerParams.getOrElse(SerialTLManagerParams(memParams = up(ExtMem).get.master))
       .copy(memParams = up(ExtMem).get.master, isMemoryDevice = true))
   )}
 })
 
 class WithSerialTLROM extends Config((site, here, up) => {
   case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
-    serialManagerParams = k.serialManagerParams.map { s => s.copy(
+    serialTLManagerParams = k.serialTLManagerParams.map { s => s.copy(
       romParams = Some(SerialTLROMParams())
     )}
   )}
 })
 
 class WithSerialTLROMFile(file: String) extends Config((site, here, up) => {
   case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
-    serialManagerParams = k.serialManagerParams.map { s => s.copy(
+    serialTLManagerParams = k.serialTLManagerParams.map { s => s.copy(
       romParams = s.romParams.map(_.copy(contentFileName = Some(file)))
     )}
   )}

diff --git a/src/main/scala/PeripheryTLSerial.scala b/src/main/scala/PeripheryTLSerial.scala
@@ -46,10 +46,10 @@ case class SerialTLAttachParams(
   slaveCrossingType: ClockCrossingType = SynchronousCrossing()
 )
 
-// The SerialTL can be configured to be bidirectional if serialManagerParams is set
+// The SerialTL can be configured to be bidirectional if serialTLManagerParams is set
 case class SerialTLParams(
   clientIdBits: Int = 8,
-  serialManagerParams: Option[SerialTLManagerParams] = None,
+  serialTLManagerParams: Option[SerialTLManagerParams] = None,
   width: Int = 4,
   attachParams: SerialTLAttachParams = SerialTLAttachParams(),
   provideClockFreqMHz: Option[Int] = None)
@@ -70,7 +70,7 @@ trait CanHavePeripheryTLSerial { this: BaseSubsystem =>
     )
     require(clientPortParams.clients.size == 1)
 
-    val managerPortParams = params.serialManagerParams.map { managerParams =>
+    val managerPortParams = params.serialTLManagerParams.map { managerParams =>
       val memParams = managerParams.memParams
       val romParams = managerParams.romParams
       val memDevice = if (managerParams.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil)
@@ -109,7 +109,7 @@ trait CanHavePeripheryTLSerial { this: BaseSubsystem =>
     serdesser.managerNode.foreach { managerNode =>
       manager.coupleTo(s"port_named_serial_tl_mem") {
         ((client.crossIn(managerNode)(ValName("TLSerialManagerCrossing")))(attachParams.slaveCrossingType)
-        := TLSourceShrinker(1 << params.serialManagerParams.get.memParams.idBits)
+        := TLSourceShrinker(1 << params.serialTLManagerParams.get.memParams.idBits)
         := TLWidthWidget(manager.beatBytes)
         := _ )
       }

diff --git a/src/main/scala/TSIHarness.scala b/src/main/scala/TSIHarness.scala
@@ -94,8 +94,8 @@ class SerialRAM(tl_serdesser: TLSerdesser)(implicit p: Parameters) extends LazyM
   ))
 
   serdesser.clientNode.foreach { clientNode =>
-    val memParams = p(SerialTLKey).get.serialManagerParams.get.memParams
-    val romParams = p(SerialTLKey).get.serialManagerParams.get.romParams
+    val memParams = p(SerialTLKey).get.serialTLManagerParams.get.memParams
+    val romParams = p(SerialTLKey).get.serialTLManagerParams.get.romParams
     val srams = AddressSet.misaligned(memParams.base, memParams.size).map { aset =>
       LazyModule(new TLRAM(
         aset,
@@ -151,10 +151,10 @@ class MultiClockSerialAXIRAM(tl_serdesser: TLSerdesser)(implicit p: Parameters)
   memClkRstDomain.clockNode := memClkRstSource
 
   val (mem_axi4, memNode) = serdesser.clientNode.map { clientNode =>
-    val axiMemOverSerialTLParams = p(SerialTLKey).get.serialManagerParams.get.axiMemOverSerialTLParams.get
+    val axiMemOverSerialTLParams = p(SerialTLKey).get.serialTLManagerParams.get.axiMemOverSerialTLParams.get
     val memCrossing = axiMemOverSerialTLParams.axiClockParams.map(_.crossingType).getOrElse(SynchronousCrossing())
-    val memParams = p(SerialTLKey).get.serialManagerParams.get.memParams
-    val romParams = p(SerialTLKey).get.serialManagerParams.get.romParams
+    val memParams = p(SerialTLKey).get.serialTLManagerParams.get.memParams
+    val romParams = p(SerialTLKey).get.serialTLManagerParams.get.romParams
 
     val memXbar = memClkRstDomain { TLXbar() }
     romParams.map { romParams =>
@@ -226,7 +226,7 @@ class MultiClockSerialAXIRAM(tl_serdesser: TLSerdesser)(implicit p: Parameters)
     })
 
     // setup clock domain
-    val axiMemOverSerialTLParams = p(SerialTLKey).get.serialManagerParams
+    val axiMemOverSerialTLParams = p(SerialTLKey).get.serialTLManagerParams
       .map(_.axiMemOverSerialTLParams).flatten.getOrElse(AXIMemOverSerialTLClockParams())
     axiMemOverSerialTLParams.axiClockParams match {
       case Some(params) => {