Update to modern chisel

src/main/scala/l2shim_interface.scala

@@ -1,8 +1,8 @@
 // ported from protoacc
 package mempress
 
-import Chisel._
-import chisel3.{Printable}
+import chisel3._
+import chisel3.util._
 import freechips.rocketchip.tile._
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
@@ -17,15 +17,15 @@ class L2ReqInternal extends Bundle {
   val addr = UInt()
   val cmd = UInt()
   val size = UInt()
-  val data = UInt(width=128)
+  val data = UInt(128.W)
 }
 
 class L2RespInternal extends Bundle {
-  val data = UInt(width=128)
+  val data = UInt(128.W)
 }
 
 class L2InternalTracking extends Bundle {
-  val addrindex = UInt(width=4)
+  val addrindex = UInt(4.W)
   val tag = UInt()
 }
 
@@ -54,9 +54,9 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
   val io = IO(new Bundle {
     val userif = Flipped(new L2MemHelperBundle)
 
-    val sfence = Bool(INPUT)
+    val sfence = Input(Bool())
     val ptw = new TLBPTWIO
-    val status = Valid(new MStatus).flip
+    val status = Input(Valid(new MStatus))
   })
 
   val (dmem, edge) = outer.masterNode.out.head
@@ -81,7 +81,7 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
 
   val status = Reg(new MStatus)
   when (io.status.valid) {
-    MemPressLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt(PRV.M))
+    MemPressLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U)
     status := io.status.bits
   }
 
@@ -90,17 +90,17 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
   tlb.io.req.bits.vaddr := request_input.bits.addr
   tlb.io.req.bits.size := request_input.bits.size
   tlb.io.req.bits.cmd := request_input.bits.cmd
-  tlb.io.req.bits.passthrough := Bool(false)
+  tlb.io.req.bits.passthrough := false.B
   val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss
 
   io.ptw <> tlb.io.ptw
   tlb.io.ptw.status := status
   tlb.io.sfence.valid := io.sfence
-  tlb.io.sfence.bits.rs1 := Bool(false)
-  tlb.io.sfence.bits.rs2 := Bool(false)
-  tlb.io.sfence.bits.addr := UInt(0)
-  tlb.io.sfence.bits.asid := UInt(0)
-  tlb.io.kill := Bool(false)
+  tlb.io.sfence.bits.rs1 := false.B
+  tlb.io.sfence.bits.rs2 := false.B
+  tlb.io.sfence.bits.addr := 0.U
+  tlb.io.sfence.bits.asid := 0.U
+  tlb.io.kill := false.B
 
 
   val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4))
@@ -119,13 +119,13 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
     }
   }
 
-  val addr_mask_check = (UInt(0x1, 64.W) << request_input.bits.size) - UInt(1)
-  val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === UInt(0)))
+  val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U
+  val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === 0.U))
   assert(assertcheck,
     printInfo + " L2IF: access addr must be aligned to write width\n")
 
   val global_memop_accepted = RegInit(0.U(64.W))
-  when (io.userif.req.fire()) {
+  when (io.userif.req.fire) {
     global_memop_accepted := global_memop_accepted + 1.U
   }
 
@@ -143,7 +143,7 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
   assert(assert_free_outstanding_op_slots,
     printInfo + " L2IF: Too many outstanding requests for tag count.\n")
 
-  when (request_input.fire()) {
+  when (request_input.fire) {
     global_memop_sent := global_memop_sent + 1.U
   }
 
@@ -162,10 +162,10 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
     dmem.a.bits := bundle
   } .elsewhen (request_input.valid) {
 
-    assert(Bool(false), "ERR")
+    assert(false.B, "ERR")
   }
 
-  val tl_resp_queues = Vec.fill(outer.numOutstandingRequestsAllowed)(
+  val tl_resp_queues = VecInit.fill(outer.numOutstandingRequestsAllowed)(
     Module(new Queue(new L2RespInternal, 4, flow=true)).io)
 
   val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready
@@ -189,7 +189,7 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
   tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid)
 
 
-  when (dmem.a.fire()) {
+  when (dmem.a.fire) {
     when (request_input.bits.cmd === M_XRD) {
       MemPressLogger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n",
         request_input.bits.addr,
@@ -262,7 +262,7 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
   }
 
 
-  when (dmem.d.fire()) {
+  when (dmem.d.fire) {
     when (edge.hasData(dmem.d.bits)) {
       MemPressLogger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n",
         dmem.d.bits.data,
@@ -275,18 +275,18 @@ class L2MemHelperModule(outer: L2MemHelper, printInfo: String = "", queueRequest
       }
   }
 
-  when (response_output.fire()) {
+  when (response_output.fire) {
     MemPressLogger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n",
       resultdata,
       global_memop_resp_to_user,
       outstanding_req_addr.io.deq.bits.tag)
   }
 
-  when (dmem.d.fire()) {
+  when (dmem.d.fire) {
     global_memop_ackd := global_memop_ackd + 1.U
   }
 
-  when (response_output.fire()) {
+  when (response_output.fire) {
     global_memop_resp_to_user := global_memop_resp_to_user + 1.U
   }
 

src/main/scala/util.scala

@@ -1,6 +1,6 @@
 package mempress
 
-import Chisel._
+import chisel3._
 import chisel3.{Printable}
 import freechips.rocketchip.tile._
 import org.chipsalliance.cde.config._