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Bitstream is generated with no issue. However, when I flash the bitstream, messages from the bootrom (e.g., CMD and LOADING ... PAYLOAD_SIZE_B) are not printed on the screen.
Expected Behavior
At least the bootrom should work properly.
Other Information
I noticed that the makefile of the bootroom (fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile) hardcoded to build bootrom image for march=rv64ima.
Even if I fixed it myself as follows, it still does not work.
From Ibex wrapping code, I also noticed that the chipyard supports for only simulation (correct me if I'm wrong).
I'm willing to contribute to make Ibex available on VCU118 with a little help from someone who are farmilar with this kind of issue :D
The text was updated successfully, but these errors were encountered:
Background Work
Chipyard Version and Hash
Release: 1.5.0
Hash: a6a6a6
OS Setup
Ex: Output of
uname -a
+lsb_release -a
+printenv
+conda list
Other Setup
Ex: Prior steps taken / Documentation Followed / etc...
Create a config for Ibex on VCU118 as follows:
Current Behavior
Bitstream is generated with no issue. However, when I flash the bitstream, messages from the bootrom (e.g., CMD and LOADING ... PAYLOAD_SIZE_B) are not printed on the screen.
Expected Behavior
At least the bootrom should work properly.
Other Information
I noticed that the makefile of the bootroom (
fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile
) hardcoded to build bootrom image formarch=rv64ima
.Even if I fixed it myself as follows, it still does not work.
From Ibex wrapping code, I also noticed that the chipyard supports for only simulation (correct me if I'm wrong).
I'm willing to contribute to make Ibex available on VCU118 with a little help from someone who are farmilar with this kind of issue :D
The text was updated successfully, but these errors were encountered: