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If those files are removed from the VCS command, it compiles the simulator successfully. These files are listed in vlis/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/sim-inputs.yml for the parameter sim.input.input_files.
Thanks for the fast reply, I can confirm that the error is fixed with those changes merged (01a03f5). I saw the PR but though it was unrelated because of the different error messages.
Now I get #1265 when running with *-debug, but that should be unrelated and a setup problem on my end. With the VPD format it works.
Background Work
Chipyard Version and Hash
Release: 1.9.0
Hash: 7475bfb
OS Setup
Linux 4.18.0-425.19.2.el8_7.x86_64 #1 SMP Tue Apr 4 05:30:47 EDT 2023 x86_64 GNU/Linux
plain 1.9 conda
Other Setup
VCS Version 2022-23/2022.06-SP2
Current Behavior
VLSI command:
make sim-syn CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
The
sim-rtl
target works fine butsim-syn
andsim-par
targets produce errors, e.g.:Similar errors are reported for other files, including
If those files are removed from the VCS command, it compiles the simulator successfully. These files are listed in
vlis/build/chipyard.TestHarness.TinyRocketConfig-ChipTop/sim-inputs.yml
for the parametersim.input.input_files
.Expected Behavior
The simulator is built successfully.
Other Information
hammer.log
Standard ASAP7 flow, worked for 1.7.1, only changes where to the
env.yml
to set path and version of VCS/Cadence tools.The text was updated successfully, but these errors were encountered: