MMIO and front bus port not generated in MMIOScratchpadOnlyRocketConfig

[zephray]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

Chipyard Version and Hash

Release: not on a release
Hash: 26f86d

OS Setup

Linux wenting-b650m 5.19.0-35-generic #36-Ubuntu SMP PREEMPT_DYNAMIC Fri Feb 3 18:36:56 UTC 2023 x86_64 GNU/Linux

No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 22.10
Release: 22.10
Codename: kinetic

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

When generating SV/ Verilog output for the provided "MMIOScratchpadOnlyRocketConfig" in sims/verilator by running make CONFIG=MMIOScratchpadOnlyRocketConfig verilog, no MMIO port or front port is generated in the output:

module ChipTop(
  input         serial_tl_bits_in_valid,
  input  [31:0] serial_tl_bits_in_bits,
  input         serial_tl_bits_out_ready,
                custom_boot,
                clock_clock,
                reset,
                jtag_TCK,
                jtag_TMS,
                jtag_TDI,
                uart_0_rxd,
  output        serial_tl_clock,
                serial_tl_bits_in_ready,
                serial_tl_bits_out_valid,
  output [31:0] serial_tl_bits_out_bits,
  output        jtag_TDO,
                uart_0_txd
);

Expected Behavior

Even though these signals might be tied off in the harness, they should be kept with dut.dontTouchPorts() inside TestHarness.scala, not optimized out. In older version of Chipyard (version 1.8.1), this is working as intended:

module ChipTop(
  input         jtag_TCK,
  input         jtag_TMS,
  input         jtag_TDI,
  output        jtag_TDO,
  output        serial_tl_clock,
  output        serial_tl_bits_in_ready,
  input         serial_tl_bits_in_valid,
  input  [31:0] serial_tl_bits_in_bits,
  input         serial_tl_bits_out_ready,
  output        serial_tl_bits_out_valid,
  output [31:0] serial_tl_bits_out_bits,
  output        axi4_mmio_0_clock,
  output        axi4_mmio_0_reset,
  input         axi4_mmio_0_bits_aw_ready,
  output        axi4_mmio_0_bits_aw_valid,
  output [3:0]  axi4_mmio_0_bits_aw_bits_id,
  output [30:0] axi4_mmio_0_bits_aw_bits_addr,
  output [7:0]  axi4_mmio_0_bits_aw_bits_len,
  output [2:0]  axi4_mmio_0_bits_aw_bits_size,
  output [1:0]  axi4_mmio_0_bits_aw_bits_burst,
  output        axi4_mmio_0_bits_aw_bits_lock,
  output [3:0]  axi4_mmio_0_bits_aw_bits_cache,
  output [2:0]  axi4_mmio_0_bits_aw_bits_prot,
  output [3:0]  axi4_mmio_0_bits_aw_bits_qos,
  input         axi4_mmio_0_bits_w_ready,
  output        axi4_mmio_0_bits_w_valid,
  output [63:0] axi4_mmio_0_bits_w_bits_data,
  output [7:0]  axi4_mmio_0_bits_w_bits_strb,
  output        axi4_mmio_0_bits_w_bits_last,
  output        axi4_mmio_0_bits_b_ready,
  input         axi4_mmio_0_bits_b_valid,
  input  [3:0]  axi4_mmio_0_bits_b_bits_id,
  input  [1:0]  axi4_mmio_0_bits_b_bits_resp,
  input         axi4_mmio_0_bits_ar_ready,
  output        axi4_mmio_0_bits_ar_valid,
  output [3:0]  axi4_mmio_0_bits_ar_bits_id,
  output [30:0] axi4_mmio_0_bits_ar_bits_addr,
  output [7:0]  axi4_mmio_0_bits_ar_bits_len,
  output [2:0]  axi4_mmio_0_bits_ar_bits_size,
  output [1:0]  axi4_mmio_0_bits_ar_bits_burst,
  output        axi4_mmio_0_bits_ar_bits_lock,
  output [3:0]  axi4_mmio_0_bits_ar_bits_cache,
  output [2:0]  axi4_mmio_0_bits_ar_bits_prot,
  output [3:0]  axi4_mmio_0_bits_ar_bits_qos,
  output        axi4_mmio_0_bits_r_ready,
  input         axi4_mmio_0_bits_r_valid,
  input  [3:0]  axi4_mmio_0_bits_r_bits_id,
  input  [63:0] axi4_mmio_0_bits_r_bits_data,
  input  [1:0]  axi4_mmio_0_bits_r_bits_resp,
  input         axi4_mmio_0_bits_r_bits_last,
  output        axi4_fbus_0_clock,
  output        axi4_fbus_0_bits_aw_ready,
  input         axi4_fbus_0_bits_aw_valid,
  input  [7:0]  axi4_fbus_0_bits_aw_bits_id,
  input  [31:0] axi4_fbus_0_bits_aw_bits_addr,
  input  [7:0]  axi4_fbus_0_bits_aw_bits_len,
  input  [2:0]  axi4_fbus_0_bits_aw_bits_size,
  input  [1:0]  axi4_fbus_0_bits_aw_bits_burst,
  input         axi4_fbus_0_bits_aw_bits_lock,
  input  [3:0]  axi4_fbus_0_bits_aw_bits_cache,
  input  [2:0]  axi4_fbus_0_bits_aw_bits_prot,
  input  [3:0]  axi4_fbus_0_bits_aw_bits_qos,
  output        axi4_fbus_0_bits_w_ready,
  input         axi4_fbus_0_bits_w_valid,
  input  [63:0] axi4_fbus_0_bits_w_bits_data,
  input  [7:0]  axi4_fbus_0_bits_w_bits_strb,
  input         axi4_fbus_0_bits_w_bits_last,
  input         axi4_fbus_0_bits_b_ready,
  output        axi4_fbus_0_bits_b_valid,
  output [7:0]  axi4_fbus_0_bits_b_bits_id,
  output [1:0]  axi4_fbus_0_bits_b_bits_resp,
  output        axi4_fbus_0_bits_ar_ready,
  input         axi4_fbus_0_bits_ar_valid,
  input  [7:0]  axi4_fbus_0_bits_ar_bits_id,
  input  [31:0] axi4_fbus_0_bits_ar_bits_addr,
  input  [7:0]  axi4_fbus_0_bits_ar_bits_len,
  input  [2:0]  axi4_fbus_0_bits_ar_bits_size,
  input  [1:0]  axi4_fbus_0_bits_ar_bits_burst,
  input         axi4_fbus_0_bits_ar_bits_lock,
  input  [3:0]  axi4_fbus_0_bits_ar_bits_cache,
  input  [2:0]  axi4_fbus_0_bits_ar_bits_prot,
  input  [3:0]  axi4_fbus_0_bits_ar_bits_qos,
  input         axi4_fbus_0_bits_r_ready,
  output        axi4_fbus_0_bits_r_valid,
  output [7:0]  axi4_fbus_0_bits_r_bits_id,
  output [63:0] axi4_fbus_0_bits_r_bits_data,
  output [1:0]  axi4_fbus_0_bits_r_bits_resp,
  output        axi4_fbus_0_bits_r_bits_last,
  input         custom_boot,
  input         clock_clock,
  input         reset,
  output        uart_0_txd,
  input         uart_0_rxd
);

Other Information

No response

[jerryz123]

This looks like it's fixed right now on the master branch. We'll push a release by the end of the week.

[zephray]

Hi, thanks for your quick reply! However I am already on the latest main branch (#26f86d). Maybe I am missing something, or the behavior is actually expected and the old 1.8.1 release behavior is wrong?

[jerryz123]

No, it should definitely be generating ports...this is what I see on 9ef3001 :

module ChipTop(                                                                                                      
  input         serial_tl_bits_in_valid,                                                                             
  input  [31:0] serial_tl_bits_in_bits,                                                                              
  input         serial_tl_bits_out_ready,                                                                            
                axi4_mmio_0_bits_aw_ready,                                                                           
                axi4_mmio_0_bits_w_ready,                                                                            
                axi4_mmio_0_bits_b_valid,                                                                            
  input  [3:0]  axi4_mmio_0_bits_b_bits_id,                                                                          
  input  [1:0]  axi4_mmio_0_bits_b_bits_resp,                                                                        
  input         axi4_mmio_0_bits_ar_ready,                                                                           
                axi4_mmio_0_bits_r_valid,                                                                            
  input  [3:0]  axi4_mmio_0_bits_r_bits_id,                                                                          
  input  [63:0] axi4_mmio_0_bits_r_bits_data,                                                                        
  input  [1:0]  axi4_mmio_0_bits_r_bits_resp,                                                                        
  input         axi4_mmio_0_bits_r_bits_last,                                                                        
                custom_boot,                                                                                         
                clock_clock,                                                                                         
                reset,                                                                                               
                jtag_TCK,                                                                                            
                jtag_TMS,                                                                                            
                jtag_TDI,                                                                                            
                uart_0_rxd,                                                                                          
  output        serial_tl_clock,                                                                                     
                serial_tl_bits_in_ready,                                                                             
                serial_tl_bits_out_valid,                                                                            
  output [31:0] serial_tl_bits_out_bits,                                                                             
  output        axi4_mmio_0_clock,                                                                                   
                axi4_mmio_0_reset,                                                                                   
                axi4_mmio_0_bits_aw_valid,                                                                           
  output [3:0]  axi4_mmio_0_bits_aw_bits_id,                                                                         
  output [30:0] axi4_mmio_0_bits_aw_bits_addr,                                                                       
  output [7:0]  axi4_mmio_0_bits_aw_bits_len,                                                                        
  output [2:0]  axi4_mmio_0_bits_aw_bits_size,                                                                       
  output [1:0]  axi4_mmio_0_bits_aw_bits_burst,                                                                      
  output        axi4_mmio_0_bits_aw_bits_lock,                                                                       
  output [3:0]  axi4_mmio_0_bits_aw_bits_cache,                                                                        output [2:0]  axi4_mmio_0_bits_aw_bits_prot,                                                                         output [3:0]  axi4_mmio_0_bits_aw_bits_qos,                                                                          output        axi4_mmio_0_bits_w_valid,                                                                              output [63:0] axi4_mmio_0_bits_w_bits_data,                                                                          output [7:0]  axi4_mmio_0_bits_w_bits_strb,                                                                          output        axi4_mmio_0_bits_w_bits_last,                                                                                        axi4_mmio_0_bits_b_ready,                                                                                            axi4_mmio_0_bits_ar_valid,                                                                             output [3:0]  axi4_mmio_0_bits_ar_bits_id,                                                                           output [30:0] axi4_mmio_0_bits_ar_bits_addr,                                                                         output [7:0]  axi4_mmio_0_bits_ar_bits_len,                                                                        
  output [2:0]  axi4_mmio_0_bits_ar_bits_size,                                                                       
  output [1:0]  axi4_mmio_0_bits_ar_bits_burst,                                                                      
  output        axi4_mmio_0_bits_ar_bits_lock,                                                                       
  output [3:0]  axi4_mmio_0_bits_ar_bits_cache,
  output [2:0]  axi4_mmio_0_bits_ar_bits_prot,
  output [3:0]  axi4_mmio_0_bits_ar_bits_qos,
  output        axi4_mmio_0_bits_r_ready,
                jtag_TDO,
                uart_0_txd
);

[zephray]

That's interesting, I deleted my local repo and started from scratch with 9ef3001, now I can getting the same result as you have. However, isn't this still wrong? The MMIO port is present, but the front bus port is still missing.

[kgreig87]

I'm also seeing the same issue as @zephray - DigitalTop contains a MMIO port, but is missing a Front Port.

[jerryz123]

Yeah, I'm looking into this.

[jerryz123]

The latest commit on this branch: https://github.com/ucb-bar/chipyard/pull/1399/files#diff-e72d7730b5de7057f15f513757aa310c4a51b21e8d5d0e1cb7b206b132e802d9 should fix this.

[kgreig87]

Thanks Jerry, this resolved the issue. I also like what you're adding with the custom IO cells

[zephray]

Awesome, thanks jerry, just tried and it works great! Should I close the issue or wait for the PR to be merged first?