ENABLE_CUSTOM_FIRRTL_PASS changes inferred SRAMs

[tymcauley]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

Chipyard Version and Hash

Release: main
Hash: 4f74f29

OS Setup

macOS 13.2.1

Other Setup

Check out fresh Chipyard, run ./scripts/init-submodules-no-riscv-tools.sh

Current Behavior

If you build the default RocketConfig with and without ENABLE_CUSTOM_FIRRTL_PASS=1, you will get different RTL at the end. I haven't exhaustively checked the differences, but I can see that when ENABLE_CUSTOM_FIRRTL_PASS=1, the SRAMs in top.mems.conf are much narrower.

To reproduce:

$ make -C sims/vcs ENABLE_CUSTOM_FIRRTL_PASS=1 verilog
...
$ mv sims/vcs/generated-src sims/vcs/generated-src.custom-firrtl-pass-enabled/
$ make -C sims/vcs verilog
...
$ cat sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.mems.conf
name cc_dir_ext depth 1024 width 136 ports mrw mask_gran 17
name cc_banks_0_ext depth 16384 width 64 ports rw
name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
name tag_array_ext depth 64 width 88 ports mrw mask_gran 22
name tag_array_0_ext depth 64 width 84 ports mrw mask_gran 21
name data_arrays_0_0_ext depth 512 width 128 ports mrw mask_gran 32
$ cat sims/vcs/generated-src.custom-firrtl-pass-enabled/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.mems.conf
name cc_dir_0_ext depth 1024 width 17 ports mrw mask_gran 17
name cc_banks_0_ext depth 16384 width 64 ports rw
name data_arrays_0_0_ext depth 512 width 8 ports mrw mask_gran 8
name tag_array_0_ext depth 64 width 22 ports mrw mask_gran 22
name tag_array_0_0_ext depth 64 width 21 ports mrw mask_gran 21
name data_arrays_0_0_0_ext depth 512 width 32 ports mrw mask_gran 32

You can see that each SRAM is much narrower (the width field is smaller) for the design where ENABLE_CUSTOM_FIRRTL_PASS=1. It looks like the design instantiates several parallel instances of each SRAM to make up the same design as when ENABLE_CUSTOM_FIRRTL_PASS is unset.

I'm not sure if the two designs are functionally identical, but even if they are, using narrower SRAMs could be a problem if users were hoping to use particular foundry SRAMs with wider entries.

Expected Behavior

I would expect the ENABLE_CUSTOM_FIRRTL_PASS=1 build to produce the same Verilog for the RocketConfig as when ENABLE_CUSTOM_FIRRTL_PASS is unset.

Other Information

I think this is the same issue as noted here: #1239 (comment)