Merge pull request #1585 from ucb-bar/enable-precommit

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ucb-bar · Aug 30, 2023 · 49b51ba · 49b51ba
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diff --git a/docs/Advanced-Concepts/Architectural-Checkpoints.rst b/docs/Advanced-Concepts/Architectural-Checkpoints.rst
@@ -36,4 +36,3 @@ The target config should also match the architectural configuration of however s
 
    cd sims/vcs
    make CONFIG=dmiRocketConfig run-binary LOADARCH=../../hello.riscv.0x80000000.1000.loadarch
-
diff --git a/docs/Advanced-Concepts/Harness-Clocks.rst b/docs/Advanced-Concepts/Harness-Clocks.rst
@@ -21,4 +21,3 @@ Take the following example:
     :end-before: DOC include end: HarnessClockInstantiatorEx
 
 Here you can see the ``th.harnessClockInstantiator`` is used to request a clock and reset at ``memFreq`` frequency.
-
diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst
@@ -52,7 +52,7 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file.
 
 You can then import the classes defined in the submodule in a new project if
 you add it as a dependency. For instance, if you want to use this code in
-the ``chipyard`` project, add your project to the list of sub-projects in the 
+the ``chipyard`` project, add your project to the list of sub-projects in the
 `.dependsOn()` for `lazy val chipyard`. The original code may change over time, but it
 should look something like this:
 

diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst
@@ -112,4 +112,3 @@ For instance, if we wanted to add the previously defined accelerator and route c
       new RocketConfig)
 
 To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``.
-
diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst
@@ -16,7 +16,7 @@ Peripheral Devices Overview
 ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
 
 These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
-All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device. 
+All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
 
 Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC.
 When adding a top-level IO, you should also be aware of whether it interacts with the test-harness.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
 General Purpose I/Os (GPIO) Device
 ----------------------------------
 
-GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers. 
+GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
 
 
 GPIO main features
@@ -67,7 +67,7 @@ Including GPIO in the SoC
       //   Set up Memory Devices
       // ==================================
       // ...
-      
+
       // Peripheral section
       new chipyard.config.WithGPIO(address = 0x10010000, width = 32) ++
 
@@ -115,7 +115,7 @@ Including UART in the SoC
       //   Set up Memory Devices
       // ==================================
       // ...
-      
+
       // Peripheral section
       new chipyard.config.WithUART(address = 0x10020000, baudrate = 115200) ++
 
@@ -125,7 +125,7 @@ Including UART in the SoC
 Inter-Integrated Circuit (I2C) Interface Device
 -------------------------------------------------
 
-I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). 
+I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
 
 
 I2C main features
@@ -158,7 +158,7 @@ Including I2C in the SoC
       //   Set up Memory Devices
       // ==================================
       // ...
-      
+
       // Peripheral section
       new chipyard.config.WithI2C(address = 0x10040000) ++
 
@@ -169,9 +169,9 @@ Including I2C in the SoC
 Serial Peripheral Interface (SPI) Device
 -------------------------------------------------
 
-SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol. 
+SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
 
-The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device. 
+The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
 
 
 SPI main features
@@ -208,7 +208,7 @@ Including SPI in the SoC
       //   Set up Memory Devices
       // ==================================
       // ...
-      
+
       // Peripheral section
       new chipyard.config.WithSPI(address = 0x10031000) ++
 

diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst
@@ -187,7 +187,7 @@ During verilog creation, a graphml file is emitted that will allow you to visual
 
 To view the graph, first download a viewer such as `yEd <https://www.yworks.com/products/yed/>`__.
 
-The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer. 
+The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer.
 To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings.
 
 .. _sw-sim-verilator-opts:

diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst
@@ -8,7 +8,7 @@ Hammer Development and Upgrades
 If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
 
 .. code-block:: shell
-    
+
     pip install -e <path/to/hammer>
 
 To bump specific plugins to their latest commits and install them, you can use the upgrade script from the Chipyard root directory, with arguments for match patterns for the plugin names:
@@ -120,7 +120,7 @@ The given example in ``UPFInputs`` corresponds to a dual-core Rocket config with
 To run the flow:
 
 .. code-block:: shell
-    
+
     cd chipyard/vlsi
     make verilog ASPECTS=chipyard.upf.ChipTopUPFAspect
 

diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst
@@ -48,7 +48,7 @@ Prerequisites
 * Python 3.9+
 * Genus, Innovus, Voltus, VCS, and Calibre licenses
 * Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
-* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__ 
+* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__
 
   * These SRAM macros were generated using the `Sram22 SRAM generator  <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
 
@@ -75,7 +75,7 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
 
 to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
 
-Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. 
+Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
 We will summarize a few files in this directory that will be important for the rest of the tutorial.
 
 .. code-block:: shell
@@ -123,7 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
 and (2) the mapping of memory instances in the design to SRAM macros;
 all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
 Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows 
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
 (due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
 chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
 

diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
@@ -55,7 +55,7 @@ Prerequisites
   * NetGen (LVS), , install `using conda <https://anaconda.org/litex-hub/netgen>`__ or `from source <http://www.opencircuitdesign.com/netgen/install.html>`__
 
 * Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
-* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__ 
+* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__
 
   * These SRAM macros were generated using the `Sram22 SRAM generator  <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
 
@@ -86,10 +86,10 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
 
     ./scripts/init-vlsi.sh sky130 openroad
 
-to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder, 
+to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
 and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
 
-Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. 
+Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
 We will summarize a few files in this directory that will be important for the rest of the tutorial.
 
 .. code-block:: shell
@@ -151,7 +151,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
 and (2) the mapping of memory instances in the design to SRAM macros;
 all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
 Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows 
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
 (due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
 chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
 
@@ -188,7 +188,7 @@ Place-and-Route
     make par tutorial=sky130-openroad
 
 Note that sometimes OpenROAD freezes on commands following the ``detailed_route`` step,
-so for now we recomment running place-and-route until the ``extraction`` step, 
+so for now we recomment running place-and-route until the ``extraction`` step,
 then re-starting the flow at this step. See the :ref:`VLSI/Sky130-OpenROAD-Tutorial:VLSI Flow Control` documentation
 below for how to break up the flow into these steps.
 
@@ -273,7 +273,7 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
       make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
       make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
 
-      # the following two commands are equivalent because the extraction 
+      # the following two commands are equivalent because the extraction
       #   step immediately precedes the write_design step
       make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
       make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"

diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc
@@ -424,7 +424,7 @@ extern "C" void cospike_cosim(long long int cycle,
     bool vector_wb = false;
     uint32_t vector_cnt = 0;
     std::vector<reg_t> vector_rds;
-    
+
     for (auto &regwrite : log) {
 
       //TODO: scaling to multi issue reads?

diff --git a/generators/chipyard/src/main/resources/vsrc/spiketile.v b/generators/chipyard/src/main/resources/vsrc/spiketile.v
@@ -286,10 +286,10 @@ module SpikeBlackBox #(
    wire                                                    __tcm_d_ready;
    bit                                                     __tcm_d_valid;
    longint                                                 __tcm_d_data;
-   
+
    reg                                                     __tcm_d_valid_reg;
    reg [63:0]                                              __tcm_d_data_reg;
-   
+
 
 
    always @(posedge clock) begin
@@ -429,7 +429,7 @@ module SpikeBlackBox #(
 
          __tcm_d_valid_reg <= __tcm_d_valid;
          __tcm_d_data_reg <= __tcm_d_data;
-         
+
       end
    end // always @ (posedge clock)
    assign insns_retired = __insns_retired_reg;

diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -91,4 +91,3 @@ class SimplePllConfiguration(
    }
    def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1
 }
-
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -45,4 +45,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
     }): _*)
   }
 }
-
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -67,4 +67,3 @@ class dmiMediumBoomCosimConfig extends Config(
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new boom.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
-
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -92,4 +92,3 @@ class UARTTSIRocketConfig extends Config(
   new chipyard.config.WithPeripheryBusFrequency(10) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
-
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -23,7 +23,7 @@ import chipyard.{ExtTLMem}
 
 /**
   * Config fragment for adding a BootROM to the SoC
-  * 
+  *
   * @param address the address of the BootROM device
   * @param size the size of the BootROM
   * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
@@ -42,7 +42,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt =
 // DOC include start: gpio config fragment
 /**
  * Config fragment for adding a GPIO peripheral device to the SoC
- * 
+ *
  * @param address the address of the GPIO device
  * @param width the number of pins of the GPIO device
  */

diff --git a/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala b/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala
@@ -38,4 +38,3 @@ class ChipyardOptions private[stage] (
       if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
   }
 }
-
diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
@@ -210,6 +210,7 @@ cat <<EOT >> env.sh
 # line auto-generated by $0
 conda activate $CYDIR/.conda-env
 source $CYDIR/scripts/fix-open-files.sh
+pre-commit install
 EOT
 
 echo "Setup complete!"

diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh
@@ -138,4 +138,3 @@ rm -rf mem.0x80000000.bin
 
 riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF
 rm -rf $RAWMEM_ELF
-
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
@@ -3,7 +3,7 @@ index 302d99e6..0aa0fcb4 100644
 --- a/build.sbt
 +++ b/build.sbt
 @@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
- 
+
  lazy val chipyard = (project in file("generators/chipyard"))
    .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
@@ -14,7 +14,7 @@ index 302d99e6..0aa0fcb4 100644
 @@ -220,10 +220,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
    .settings(libraryDependencies ++= rocketLibDeps.value)
    .settings(commonSettings)
- 
+
 -lazy val sha3 = (project in file("generators/sha3"))
 -  .dependsOn(rocketchip, midasTargetUtils)
 -  .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -23,6 +23,6 @@ index 302d99e6..0aa0fcb4 100644
 +//   .dependsOn(rocketchip, midasTargetUtils)
 +//   .settings(libraryDependencies ++= rocketLibDeps.value)
 +//   .settings(commonSettings)
- 
+
  lazy val gemmini = (project in file("generators/gemmini"))
    .dependsOn(rocketchip)
diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py
@@ -201,7 +201,7 @@ def main():
   # write model filelist
   write_verilog_filelist(uniquified_modules_under_model, verilog_module_filename, args.out_model_filelist)
   write_cc_filelist     (cc_filelist, args.out_model_filelist)
-  
+
 
 if __name__=="__main__":
   main()
diff --git a/sims/xcelium/.gitignore b/sims/xcelium/.gitignore
@@ -1,3 +1,3 @@
 *
 !.gitignore
-*Makefile
+*Makefile
diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle
@@ -27,4 +27,3 @@ done
 target_args="$target_args +permissive-off"
 
 INPUT_ARGS="$regular_args $target_args"
-
diff --git a/sims/xcelium/xcelium.mk b/sims/xcelium/xcelium.mk
@@ -62,4 +62,3 @@ PREPROC_DEFINES = \
 	-define RANDOMIZE_REG_INIT \
 	-define RANDOMIZE_GARBAGE_ASSIGN \
 	-define RANDOMIZE_INVALID_ASSIGN
-
diff --git a/software/embench/build.sh b/software/embench/build.sh
@@ -20,4 +20,3 @@ for bmark in "${bmarks[@]}"
 do
     cp bd/src/$bmark/$bmark $BUILDDIR/
 done
-
diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml
@@ -9,7 +9,7 @@ vlsi.inputs.clocks: [
 # If overriding the placement constraints in example-sky130.yml,
 # ensure one of the toplevel margin sides corresponding with the power pin metal layers
 # is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
-# For example, in example-sky130.yml we set 
+# For example, in example-sky130.yml we set
 #   par.generate_power_straps_options.by_tracks.pin_layers: 'met5'  # horizontal layer
 # therefore we must also set:
 #   vlsi.inputs.placement_constraints:

diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -44,7 +44,7 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 1250
     orientation: r90
- 
+
   # tag array
   - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro

diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml
@@ -28,7 +28,7 @@ par.openroad:
   clock_tree_resize.setup_margin: 0.0
   clock_tree_resize.hold_margin: 0.20
   global_route_resize.hold_margin: 0.60
-  clock_tree_resize.hold_max_buffer_percent: 80  
+  clock_tree_resize.hold_max_buffer_percent: 80
 
   global_placement.routing_adjustment: 0.5
   global_route.routing_adjustment: 0.3
@@ -76,7 +76,7 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 1250
     orientation: r90
- 
+
   # tag array
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro