MERGE: merge from main

.github/workflows/make-examples.yaml

@@ -25,14 +25,16 @@ jobs:
         tar -xf riscv64-unknown-toolchain.tar.xz
     - name: Make default
       run: |
+        rm -rf ./build/
         export RISCV="$GITHUB_WORKSPACE/riscv64-unknown-toolchain"
         export PATH="$RISCV/bin:$PATH"
-        cmake . -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake
+        cmake -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake
         cmake --build ./build/ --target app
     - name: Make for BearlyML
       run: |
+        rm -rf ./build/
         export RISCV="$GITHUB_WORKSPACE/riscv64-unknown-toolchain"
         export PATH="$RISCV/bin:$PATH"
-        cmake . -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake -D CHIP=bearlyml
+        cmake -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake -D CHIP=bearlyml
         cmake --build ./build/ --target app
 

CMakeLists.txt

@@ -50,15 +50,23 @@ set(ARCH_FLAGS          -march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL})
 set(SPECS               "nosys.specs")
 set(SPEC_FLAGS          -specs=${SPECS})
 
+
+# convert CHIP to lowercase
+string(TOLOWER ${CHIP} CHIP)
+
 # linker script
 # HACK: ideally this should be handled by glossy, but currently i couldn't 
 # figure out a way to propagate the LINKER_SCRIPT variable to the compile and link commands
 if (NOT CHIP)
+  message(STATUS "Chip not specified, using default configuration")
+  set(CHIP "default")
+
   set(LINKER_SCRIPT       "${CMAKE_SOURCE_DIR}/glossy/glossy.ld")
 else()
   set(LINKER_SCRIPT       "${CMAKE_SOURCE_DIR}/platform/${CHIP}/${CHIP}.ld")
 endif()
 
+add_subdirectory(${CMAKE_SOURCE_DIR}/platform/${CHIP})
 
 add_compile_options(-O1)
 add_compile_options(-Wall -Wextra)
@@ -86,7 +94,7 @@ add_executable(app
   app/src/main.c
 )
 
-target_include_directories(app PUBLIC app/inc)
+target_include_directories(app PUBLIC app/include)
 
 
 #################################

driver/CMakeLists.txt

@@ -3,6 +3,8 @@ add_subdirectory(metal)
 
 add_subdirectory(htif)
 
+add_subdirectory(intel/pll)
+
 add_subdirectory(national-semiconductor/ns16550a)
 
 add_subdirectory(rocket-chip/clint)

driver/htif/CMakeLists.txt

@@ -4,3 +4,7 @@ add_library(htif STATIC htif.c)
 target_include_directories(htif PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
 
 target_link_libraries(htif PUBLIC metal)
+
+message(STATUS "Including HTIF to target")
+
+set(HTIF_ENABLED ON)

driver/htif/atomic.h

@@ -1,7 +1,8 @@
-#ifndef __RV_ATOMIC_H
-#define __RV_ATOMIC_H
+#ifndef __ATOMIC_H
+#define __ATOMIC_H
 
 #include <stdint.h>
+#include "metal.h"
 
 static inline unsigned long local_irq_save(void) {
   /* Interrupts are currently always disabled in M-mode */
@@ -25,12 +26,12 @@ static inline void mb_release(void) { fence(rw, w); }
 typedef int32_t atomic_t;
 
 static inline long atomic_load(const atomic_t *p) {
-    /* FIXME: Elide redundant sext.w for volatile variables */
-    return *((volatile const atomic_t *)p);
+  /* FIXME: Elide redundant sext.w for volatile variables */
+  return *((__I atomic_t *)p);
 }
 
 static inline void atomic_store(atomic_t *p, atomic_t v) {
-    *((volatile atomic_t *)p) = v;
+  *((__O atomic_t *)p) = v;
 }
 
 static inline long atomic_swap_acquire(atomic_t *p, atomic_t v) {
@@ -65,4 +66,4 @@ static inline void atomic_clear_release(atomic_t *p) {
   #endif
 }
 
-#endif /* __RV_ATOMIC_H */
+#endif /* __ATOMIC_H */

driver/htif/htif.h

@@ -32,10 +32,8 @@ typedef struct {
   __IO uint64_t *fromhost;
 } HTIF_Type;
 
-#ifndef HTIF
-  extern HTIF_Type htif_handler;
-  #define HTIF (&htif_handler)
-#endif
+extern HTIF_Type htif_handler;
+#define HTIF (&htif_handler)
 
 long htif_syscall(uint64_t a0, uint64_t a1, uint64_t a2, unsigned long n);
 

driver/htif/spinlock.h

@@ -1,5 +1,5 @@
-#ifndef _CHIPYARD_SPINLOCK_H
-#define _CHIPYARD_SPINLOCK_H
+#ifndef __SPINLOCK_H
+#define __SPINLOCK_H
 
 #include "atomic.h"
 
@@ -14,11 +14,12 @@ static inline void spin_lock(spinlock_t *lock) {
     #ifdef __riscv_atomic
       while (atomic_load(&lock->lock));
     #endif
-  } while (atomic_swap_acquire(&lock->lock, -1));
+  }
+  while (atomic_swap_acquire(&lock->lock, -1));
 }
 
 static inline void spin_unlock(spinlock_t *lock) {
   atomic_clear_release(&lock->lock);
 }
 
-#endif /* _CHIPYARD_SPINLOCK_H */
+#endif /* __SPINLOCK_H */

driver/intel/pll/CMakeLists.txt

@@ -0,0 +1,6 @@
+
+add_library(intel-pll STATIC pll.c)
+
+target_include_directories(intel-pll PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
+
+target_link_libraries(intel-pll PUBLIC metal)

driver/intel/pll/pll.c

@@ -0,0 +1,2 @@
+
+#include "pll.h"

driver/intel/pll/pll.h

@@ -0,0 +1,84 @@
+#ifndef __PLL_H
+#define __PLL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "metal.h"
+
+
+typedef struct {
+  __IO uint32_t FZ_TIGHT_LOOPB;                         // 0x00
+  __IO uint32_t FZ_LOCKFORCE;                           // 0x04
+  __IO uint32_t FZ_LOCKCNT;                             // 0x08
+  __IO uint32_t FZ_LOCKTHRESH;                          // 0x0C
+  __IO uint32_t FZ_PFD_PW;                              // 0x10
+  __IO uint32_t FZ_DCA_CTRL;                            // 0x14
+  __IO uint32_t FZ_DCA_CB;                              // 0x18
+  __IO uint32_t FZ_IREFGEN;                             // 0x1c
+  __IO uint32_t FZ_STARTUP;                             // 0x20
+  __IO uint32_t FZ_CP1TRIM;                             // 0x24
+  __IO uint32_t FZ_CP2TRIM;                             // 0x28
+  __IO uint32_t FZ_NOPFDPWRGATE;                        // 0x2c
+  __IO uint32_t FZ_PFDDLY;                              // 0X30
+  __IO uint32_t FZ_CPNBIAS;                             // 0X34
+  __IO uint32_t FZ_VCOTRIM;                             // 0X38
+  __IO uint32_t FZ_SKADJ;                               // 0X3C
+  __IO uint32_t FZ_VCOSEL;                              // 0X40
+  __IO uint32_t FZ_SPARE;                               // 0X44
+  __IO uint32_t FZ_LDO_FASTSTART;                       // 0x48
+  __IO uint32_t FZ_LDO_BYPASS;                          // 0x4C
+  __IO uint32_t FZ_LDO_VINVOLTSEL;                      // 0x50
+  __IO uint32_t FZ_LDO_FBTRIM;                          // 0x54
+  __IO uint32_t FZ_LDO_REFTRIM;                         // 0x58
+  __IO uint32_t POWERGOOD_VNN;                          // 0x5C
+  __IO uint32_t PLLEN;                                  // 0x60
+  __IO uint32_t LDO_ENABLE;                             // 0x64
+  __IO uint32_t BYPASS;                                 // 0x68
+  __IO uint32_t RATIO;                                  // 0x6C
+  __IO uint32_t FRACTION;                               // 0x70
+  __IO uint32_t MDIV_RATIO;                             // 0x74
+  __IO uint32_t ZDIV0_RATIO;                            // 0x78
+  __IO uint32_t ZDIV0_RATIO_P5;                         // 0x7C
+  __IO uint32_t ZDIV1_RATIO;                            // 0x80
+  __IO uint32_t ZDIV1_RATIO_P5;                         // 0x84
+  __IO uint32_t VCODIV_RATIO;                           // 0x88
+  __IO uint32_t FZ_LDO_EXTREFSEL;                       // 0x8C
+  __IO uint32_t SSC_FRAC_STEP;                          // 0x90
+  __IO uint32_t SSC_CYC_TO_PEAK_M1;                     // 0x94
+  __IO uint32_t SSC_EN;                                 // 0x98
+  __IO uint32_t MASH_ORDER_PLUS_ONE;                    // 0x9C
+  __IO uint32_t FZ_LOCKSTICKYB;                         // 0xA0
+  __IO uint32_t FZ_LPFCLKSEL;                           // 0xA4
+  __IO uint32_t IDVDISABLE_BI;                          // 0xA8
+  __IO uint32_t IDVFREQAI;                              // 0xAC
+  __IO uint32_t IDVFREQBI;                              // 0xB0
+  __IO uint32_t IDVPULSEI;                              // 0xB4
+  __IO uint32_t IDVTCLKI;                               // 0xB8
+  __IO uint32_t IDVTCTRLI;                              // 0xBC
+  __IO uint32_t IDVTDI;                                 // 0xC0
+  __IO uint32_t IDVTRESI;                               // 0xC4
+  __IO uint32_t IDFX_FSCAN_SDI;                         // 0xC8
+  __IO uint32_t IDFX_FSCAN_MODE;                        // 0xCC
+  __IO uint32_t IDFX_FSCAN_SHIFTEN;                     // 0xD0
+  __IO uint32_t IDFX_FSCAN_RSTBYPEN;                    // 0xD4
+  __IO uint32_t IDFX_FSCAN_BYPRSTB;                     // 0xD8
+  __IO uint32_t IDFX_FSCAN_CLKUNGATE;                   // 0xDC
+  __IO uint32_t TCK;                                    // 0xE0
+  __IO uint32_t TCAPTUREDR; 		                        // 0xE4
+  __IO uint32_t TDI;                                    // 0xE8
+  __IO uint32_t TREG_EN; 		                            // 0xEC
+  __IO uint32_t TRST_N; 		                            // 0xF0
+  __IO uint32_t TSHIFTDR;                               // 0xF4
+  __IO uint32_t TUPDATEDR;                              // 0xF8
+  __IO uint32_t LDO_VREF;                               // 0xFC
+  __IO uint32_t PLLFWEN_B;                              // 0x100
+} PLL_Type;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLL_H */

driver/national-semiconductor/ns16550a/ns16550a.S

@@ -11,50 +11,50 @@
 
 uart_init:
 .cfi_startproc
-    li  t0, UART_ADDRESS
+  li  t0, UART_ADDRESS
 
-    # 0x3 -> 8 bit word length
-    li  t1, 0x3
-    sb  t1, LINE_CONTROL_REGISTER(t0)
+  # 0x3 -> 8 bit word length
+  li  t1, 0x3
+  sb  t1, LINE_CONTROL_REGISTER(t0)
 
-    # 0x1 -> enable FIFOs
-    li  t1, 0x1
-    sb  t1, LINE_CONTROL_REGISTER(t0)
+  # 0x1 -> enable FIFOs
+  li  t1, 0x1
+  sb  t1, LINE_CONTROL_REGISTER(t0)
 
-    # 0x1 -> enable reciever interrupts
-    sb  t1, INTERRUPT_ENABLE_REGISTER(t0)
+  # 0x1 -> enable reciever interrupts
+  sb  t1, INTERRUPT_ENABLE_REGISTER(t0)
 
-    ret
+  ret
 .cfi_endproc
 
 uart_getc:
 .cfi_startproc
-    li      t0, UART_ADDRESS
+  li      t0, UART_ADDRESS
 
-    lbu     t1, LINE_STATUS_REGISTER(t0)
-    andi    t1, t1, LINE_STATUS_DATA_READY
+  lbu     t1, LINE_STATUS_REGISTER(t0)
+  andi    t1, t1, LINE_STATUS_DATA_READY
 
-    # jump to _uart_read if UART is ready to read from
-    bnez    t1, _uart_read
+  # jump to _uart_read if UART is ready to read from
+  bnez    t1, _uart_read
 
-    # otherwise, return 0
-    mv      a0, zero
-    j       _uart_get_end
+  # otherwise, return 0
+  mv      a0, zero
+  j       _uart_get_end
 
 _uart_read:
-    # load character at UART address into a0
-    lbu     a0, (t0)
-    j       _uart_get_end
+  # load character at UART address into a0
+  lbu     a0, (t0)
+  j       _uart_get_end
 
 _uart_get_end:
-    ret
+  ret
 .cfi_endproc
 
 uart_putc:
 .cfi_startproc
-    li  t0, UART_ADDRESS
+  li  t0, UART_ADDRESS
 
-    # store character at UART address in return register
-    sb  a0, (t0)
-    ret
+  # store character at UART address in return register
+  sb  a0, (t0)
+  ret
 .cfi_endproc

driver/rocket-chip-blocks/uart/uart.h

@@ -68,10 +68,6 @@ typedef struct {
   UART_StopBits stopbits;
 } UART_InitType;
 
-#ifndef UART0_BASE
-  #define UART0_BASE                0x10020000U
-  #define UART0                     ((UART0_Type *)UART0_BASE)
-#endif
 
 static inline uint8_t uart_get_rx_fifo_depth(UART_Type *UARTx) {
   return READ_BITS(UARTx->RXCTRL, UART_RXCTRL_RXCNT_MSK) >> UART_RXCTRL_RXCNT_POS;

driver/rocket-chip/clint/CMakeLists.txt

@@ -4,3 +4,7 @@ add_library(clint STATIC clint.c)
 target_include_directories(clint PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
 
 target_link_libraries(clint PUBLIC metal)
+
+message(STATUS "Including CLINT to target")
+
+set(CLINT_ENABLED ON)

driver/rocket-chip/clint/clint.c

@@ -1,5 +1,5 @@
 /**
- * @file hal_clint.c
+ * @file clint.c
  * @author -T.K.- / t_k_233@outlook.com
  * @brief 
  * @version 0.1

driver/rocket-chip/clint/clint.h

@@ -1,5 +1,5 @@
-#ifndef __LL_CLINT_H
-#define __LL_CLINT_H
+#ifndef __CLINT_H
+#define __CLINT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,4 +47,4 @@ void clint_set_timer_interrupt_target(CLINT_Type *clint, uint32_t hartid, uint64
 }
 #endif
 
-#endif /* __LL_CLINT_H */
+#endif /* __CLINT_H */