AMBA bus generator including AXI4, AXI3, AHB, and APB

基于verilog实现了ISP图像处理IP

IP Veriification of I2C master using the I3C VIP

This project deals with the axi4Lite protocol

APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS

Bitmap Processing Library & AXI-Stream Video Image VIP

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Designing means to communicate as an SPI master, being a part of AXI interface

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Network on Chip Implementation written in SytemVerilog

Simple template-based UVM code generator

General Purpose I/O agent written in UVM

Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

An UVM example of UART

work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework

AMBA AXI VIP

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

UVM interactive debug library

SystemVerilog UVM testbench example

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

AMBA AHB 2.0 VIP in SystemVerilog UVM

Functional verification project for the CORE-V family of RISC-V cores.

freeCodeCamp.org's open-source codebase and curriculum. Learn to code for free.

RISC-V CPU Core (RV32IM)