[AMD][BACKEND] Use PaddedLayout with AsyncCopy on gfx950 when pipelining #8365
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…ing for the smem layout dev Bank conflict free layouts for mfma32 and mfma16 with and without transpose Bank conflict free kWidth=4 Fix debug prints Put padded composition to separate function
This reverts commit 415e24c.
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Thank you for the quick review, I think I addressed all comments. The |
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37a9e80 fixes the bank conflicts for |
antiagainst
approved these changes
Oct 7, 2025
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Adds support to the AMD pipeliner to compose
PaddedSharedEncodingforttg.async_copy_global_to_localongfx950.As described in #7929 padding alone cannot avoid bank conflicts on
GFX9because due to hardware design we can only add padding at warp boundaries64 threads × 16 bytes = 1024 byteso in addition to padding we also reorder rows via thelinearComponentof thePaddedSharedEncoding.Rows are reordered to place 16 consecutive logical rows strided by 1024 bytes into shared memory. For instance, if each row is 256 bytes, the layout would look like:
[[row0], [row16], [row32], [row48], /*1024bytes*/ [row1], [row17], [row33], [row49], /*2048bytes*/ [row2], [row18] ...]The aim of those layouts is to reduce register pressure and instruction count compared to swizzled layouts at the expense of a slightly increased LDS memory footprint.
This PR includes support for
dtype==16bitsand the tensor size is >= 16KB.