[AMD][Backend, Atomics] Remove old comment regarding buffer atomics

[SamGinzburg]

Overview

I spent a day investigating an old comment in the AMD backend regarding buffer atomics (specifically buffer atomic RMW) which suggested that buffer atomics perform better on MI-* series GPUs. The branch I worked on is available here for reference.

I think that (today, maybe this was different in the past) as far as I can tell the only benefit that buffer atomics (on their own) offer is the same hardware masking benefits that other buffer ops have (i.e., atomics out of bounds are dropped). This depends on how the buffer atomics are synchronized though, and this is where I'm less sure of whats correct:

With full barriers (identical performance to "normal" atomics):

buffer_wbl2 sc1
s_waitcnt lgkmcnt(0)
atomicRMWop()
s_waitcnt vmcnt(0) 
buffer_inv sc1
buffer_wbl2 sc1
s_waitcnt lgkmcnt(0)
atomicRMWop()
s_waitcnt vmcnt(0) 
buffer_inv sc1

With some assumptions specific to gfx942 (This can improve latency in bw-bound Split-K for some but not all shapes, it seems this is what CK does):

buffer_wbl2 sc1
s_waitcnt lgkmcnt(0)
atomicRMWop()
s_waitcnt vmcnt(0) # AMDGCN specific cross-CU synchronization primitive
atomicRMWop()
s_waitcnt vmcnt(0) 
buffer_inv sc1

If there is interest, I can file a PR to add experimental support for buffer atomic RMW ops. The only major difference with my implementation is that I added support for CTA-scope (atomics in the AMD backend today only support agent scope as far as I can tell I think).

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[SamGinzburg]

@giuseros @makslevental