Control a FPGA via a Raspberry Pi and a Webserver.
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May 19, 2026 - JavaScript
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xilinx-vivado
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SPI master have been implemented using Verilog in Xilinx Vivado
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Updated
Jun 12, 2025 - JavaScript
12-state Moore FSM four-way traffic light controller in Verilog HDL with protected left turns, all-red safety interlocks, and 100MHz-to-1Hz clock divider. Deployed on Basys 3 (Artix-7).
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Updated
May 12, 2026 - JavaScript
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