Implementation of a model of pipelined MIPS processor in Verilog

A single cycle CPU running MIPS instructions on Xilinx FPGA

Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control. - Verilog

🖼✏️ My first baby steps into the world of image processing

Design and Implementation of Arithmetic Logic Unit Capable of Calculating Z=1/4(A X B)+1

VHDL Verilog / Clock on Spartan3 / 2014 University of Seoul

DES encryption implemented on FPGA using verilog

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Small project to track things with a waterproof sonar sensor

To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.

VHDL Program Examples

In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.

Running your application from DDR memory & BPI flash using SREC bootloader

These are VHDL codes that I wrote as a part of our Computer Architecture Course in the 4th Semester.

Working projects from BLOS lessons on Brno University of Technology

Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7

RISC22 is a simple 22-bit RISC CPU designed in VHDL, featuring a minimal instruction set and a pipelined architecture for efficient execution.

This repository contains three different design of binary multiplier. Array Multiplier, Carry Save Multiplier and normal multiplier.

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)