#

uvm-testbench

Here is 1 public repository matching this topic...

osaidnur / BMU-Verification

UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions

riscv systemverilog risc-v systemverilog-hdl bitmanipulation uvm-verification bitmanip uvm-testbench

Updated Sep 16, 2025
SystemVerilog

Improve this page

Add a description, image, and links to the uvm-testbench topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the uvm-testbench topic, visit your repo's landing page and select "manage topics."