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timed-petri-nets

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jnonino-crpisetta-icomp / implementacion

Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC

c fpga vhdl concurrent-programming computer-engineering verilog research-project petri-nets academic-project parallel-programming ip-core time-petri-nets timed-petri-nets

Updated Mar 6, 2023
C

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