This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.
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Updated
Sep 15, 2025 - Verilog