Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo
The Raven SOC project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 (PnR), Design Compiler NXT (Synthesis) and Prime Time (Timing Analysis) EDA tools from Synopsys, following a bottom-to-top design methodology and hierarchical design style.
The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style
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