sythesis

This project is about the implementation of a RV32I ISA based CPU in Verilog. This project's end goal is to start with a RTL Design to GDSII (Final File Format)

Mimesis's dumber cousin for Go that churns out sythetic data.

Solvothermal synthesis and characterisation of UiO-66 and UiO-66–NH₂, investigating the role of HCl modulation using PXRD, ATR–FTIR, ¹H NMR, and TGA.