Open-source SystemVerilog soft IP for FPGA-based RF waveform generation and FMCW chirps, with independent Python models, bit-exact verification, and physical validation on a Lattice CrossLink-NX FPGA.
open-source fpga dsp radar rtl systemverilog dds digital-signal-processing rf yosys risc-v signal-generation nco cocotb fmcw nextpnr lattice-fpga fmcw-waveform fmcw-radar soft-ip
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Updated
Oct 8, 2026 - SystemVerilog