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risc-v-emulator

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astrogeekdk / RISC-V-Basic-SIMD

A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.

processor-architecture processor simd simd-parallelism risc-v processor-simulator processor-design risc-v-assembly risc-v-emulator

Updated Feb 23, 2025
Scala

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