qflow

Here are 3 public repositories matching this topic...

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

open-source fsm verilog xilinx-vivado qflow rtltogds2 asicflow

Here you can find different verifications, time analysis, etc.

analysis verilog aspects qflow designs-verification

6-bit prefix adder implemented via Verilog HDL.

verilog qflow prefix-adder

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