Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.

(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.

A collection of code from CDA 4240C: Design of Digital System and Lab

This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.

Digital Electronics 1 course at Brno University of Technology

A digital locker made for Nexys A7 using Xilinx Vivado and VHSIC Hardware Description Language

A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.

Team project in BPC-DE1 course on FEEC BUT