PCB Design Language: A programming way to design schematics.

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

This is a SpyDrNet Plugin for a physical design related transformations

SKiDL Microcontroller Board Wizard

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

TMR utilities for the SpyDrNet project

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

A few experiments using the SpyDrNet netlist library.

tile-based digital logic sandbox

Perform gate-level simulations from python

S-expression data structure parser/manipulator intended for parsing and manipulating lisp program, lisp data, netlists like EDIF and KiCAD, etc.