In this Project, a sophisticated traffic light controller was developed using Verilog and was implemented on an FPGA (Field-Programmable Gate Array) platform. The primary aim was to simulate a realistic traffic management system, employing a Moore state machine design paradigm.

This project implements a Finite State Machine (FSM) in Verilog to control a simple traffic light system.The design models real-world sequential logic using a Moore machine (outputs depend only on the current state).A testbench verifies the functionality by simulating clock cycles and observing the light outputs.