COL216, Spring 2021. Building MIPS interpreter step-by-step over assignments. The last assignment is the completed interpreter. Details in reports attached.

MIPS ISA simulator which implements non-blocking DRAM access

C++ library to simulate a MIPS32 CPU.

Simple MIPS emulator implementation

Simulator for MIPS pipeline

A Mips I CPU simulation written in C++ that is completely programmable and can run most instructions.

simulator written for a subset of the MIPS instruction set

A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput

Mips Pipeline & Execution Simulator

Supports 12 MIPS instructions

Simulator for a subset of the MIPS ISA

Created a MIPS interpreter in c++ language pertaining to certain instructions

🏭 Assembler to emulate and execute programs written in MIPS assembly language independent of hardware.

MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution

A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.

The main purpose of this project is to understand MIPS Assembly language. The input of this program is a file consisting sequence of MIPS instructions in binary. This version expands the first to implement behaviour of cache. At the end of the execution, the simulator reports the number of total cache hits and misses. These programs contain 500+…

DRAM Request Manager for Multicore Processors