Toolset to capture, simulate, synthesize and verify graph models
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Updated
Oct 15, 2024 - Java
Toolset to capture, simulate, synthesize and verify graph models
Logic synthesis and ABC based optimization
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
Showcase examples for EPFL logic synthesis libraries
This is a tutorial on standard digital design flow
An open-source design automation framework for Field-coupled Nanotechnologies
C++ parsing library for simple formats used in logic synthesis and formal verification
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
DATC RDF
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
EDA physical synthesis optimization kit
The Verilog source code for DRUM approximate multiplier.
Benchmarks for Approximate Circuit Synthesis
Automated conversion from CHP to PRS using syntax-directed translation
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
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