#

litex

Here are 13 public repositories matching this topic...

rprinz08 / hBPF

hBPF = eBPF in hardware

fpga python3 ebpf litex migen

Updated Jan 27, 2023
Python

sergachev / litex-template

Template project for LiteX-based SoCs

system-on-chip litex migen

Updated May 20, 2026
Python

apfaudio / eurorack-pmod-litex

Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.

audio fpga eurorack litex ecp5

Updated Oct 7, 2025
Python

tomtor / rust-litex

Running Rust on the (Linux) Litex VexRiscv FPGA SOC

linux rust litex

Updated Jun 3, 2025
Python

labsticc-arcad / LiteInjector

LiteInjector : A LiteX based tool for emulating logical faults on Systems on Chips

linux emulation fault-injection fia litex security-evaluation fault-emulation

Updated Aug 18, 2025
Python

DerFetzer / colorlight-litex

rust ethernet risc-v litex embedded-rust

Updated Aug 9, 2021
Python

chmousset / hmmc

Hardware Motion and Motor Control Library

fpga cnc-controller bldc pmsm litex motion-control migen foc motor-control servomotor-control

Updated Jul 22, 2023
Python

freddy- / migen-playground

fpga litex migen

Updated Apr 11, 2020
Python

Mark1626 / litex-alchitry-cu-examples

Examples of using Litex on an Alchitry Cu board

fpga hardware system-on-chip litex alchitry-cu

Updated Feb 4, 2024
Python

kami4ka / tang_computer

Self-contained RISC-V Linux machine on a Sipeed Tang Primer 20K FPGA — a VexRiscv-SMP soft CPU (LiteX) running mainline 32-bit Linux, with an LCD framebuffer console and a USB keyboard driven through the dock's USB3317 PHY in 6-pin ULPI serial mode.

linux fpga framebuffer buildroot usb-host soc risc-v embedded-linux soft-core litex gowin sipeed ulpi vexriscv tang-primer-20k

Updated Jul 22, 2026
Python

tweakoz / litex-testsoc

LitexLinuxVexRiscV test SOC

linux fpga riscv soc litex

Updated Apr 13, 2020
Python

project-petalite

franos-cm / project-petalite

Proof of concept for a hardware TPM implementing CRYSTALS-Dilithium

tpm tpm2 litex dilithium crystals-dilithium

Updated Dec 17, 2025
Python

supleed2 / EIE4-FYP

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

embedded-systems systemverilog can-bus audio-synthesis risc-v cordic litex ecp5 waveform-generator vexriscv orangecrab stacksynth

Updated Jan 19, 2024
Python

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