Database of CPU Opcodes

RISC-V Assembly code assembler package for Python.

This repository contains the codebase for the MetaTransformers Fractal Workflow System, a comprehensive framework for managing and orchestrating complex workflows. The system is designed to handle a wide range of data types and workflows, from simple data processing to complex AI-driven transformations.

Instruction Set Architecture Description Format

Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"

A 64-bit stack based instruction set architecture definition with reference implementation. (The assembler is part of my C compiler that targets StackVM)

A modular general 2-pass assembler written in Python.

Mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers

Python implementation of a 32-bit processor with its own ISA (Instruction Set Architecture)

This is the implementation of an instruction-set architecture (ISA) simulator in Python. It deals with small machine language programs in order to understand the functionality and the structure of a simple processor.

18-bit processor implementation using Logisim

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

A assembler and simulator for a custom RISC ISA

A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.

Assembler implementation or the Hack computer from the Nand To Tetris course.

Python module to work with microprocessor instruction sets

Alpha v5

Testing out optimal magic numbers for the old fast inverse square root function.

Converts LEGv8 instructions to Machine Code

SAR: Simple Architecture RISC Simulator