Simulation model of a mathematical processor (Floating point unit, FPU)
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Updated
Nov 30, 2022 - Python
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fpu
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IEEE 754 half-precision (FP16) FPU in Verilog — implements Add, Sub, Mul, Div with a Python/NumPy verification pipeline. Achieves 99.7% accuracy across 10,000 randomised test cases including subnormals, overflow, and NaN edge cases.
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Updated
Apr 17, 2026 - Python
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