FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain
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Mar 1, 2021 - VHDL
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fpga-accelerator
Here are 7 public repositories matching this topic...
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
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May 22, 2023 - VHDL
🏄 Custom IP for vector operations
zynq
vector
vhdl
vivado
hardware-designs
hdl
custom-ip
fpga-accelerator
axi
vitis
axi-lite
vector-operation
vector-ops
vector-operations
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Aug 31, 2024 - VHDL
A FPGA Based Square Root Approximation Coprocessor
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Jul 13, 2020 - VHDL
University of Pittsburgh ECE 1195
fpga
hardware
finite-state-machine
vivado
hardware-acceleration
mips32cpu
fpga-accelerator
vivado-hls
vhdl-coursework
data-path
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Apr 16, 2023 - VHDL
Hardware-accelerated sorting algorithm
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Updated
May 4, 2020 - VHDL
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
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Jan 5, 2019 - VHDL
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