Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Hardware-accelerated sorting algorithm

University of Pittsburgh ECE 1195

🏄 Custom IP for vector operations

A FPGA Based Square Root Approximation Coprocessor

A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.

FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain