5-stage in-order pipeline simulator in C: IF/ID/EX/MEM/WB stages, custom 11-opcode ISA, load-use stall detection, EX/MEM and MEM/WB data forwarding, 2-cycle branch/jump flush. Direct-mapped icache and dcache (64 lines, 4-cycle miss). Outputs cycle-by-cycle latch state, timing diagrams, CPI and cache stats.
c simulator cache isa performance-analysis computer-architecture hazard-detection microarchitecture branch-prediction cpu-simulator data-forwarding pipeline-simulator in-order-pipeline-architecture
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Updated
May 8, 2026 - C