AUT Computer Architecture Cache Simulator project

A simulator for modelize cache memory of CPU.

Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory

A cache simulator that takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses, and evictions for each cache type along with the content of each cache at the end.

Simple cache simulator built using Java.

A loop test performance simulator for cache memories

Cache Simulation program for hit rate in java with 2 mappings (Direct Mapping and 4 Way Set Associative Mappings) (Main Memory Size : 4 GB, Block Size : 16 bytes, Cache size : 1 M blocks => 2^20 lines )

Trabalho da disciplina de Arquitetura e Organização de Computadores 2

Simple Cache Simulator

Cache Simulator is a Java program that simulates a simple cache system with various inputs, including cache size, replacement policy, associativity and write-back policy. 2019.

search engine simulator. Implement both the client and the server side, with emphasis on multithreaded programming and synchronization of these. Involves the use of sockets. server that efficiently handle large number of clients.

Симулятор работы кэша процессора для подсчёта процента кэш-попаданий и потраченных тактов процессора при выполнении программы, приведённой в файле test.cc Подробнее конкретные параметры (размеры кэша, такты затрачиваемые на те или иные действия) - в файле-отчёте.

Implementations of various cache strategies

Cache and memory hierarchy simulator using L1 or both L1 and L2 cache

Simulation of a memory cache (addresses only), for Computer Architecture (2021-22).

Implementação de um Simulador de Caches desenvolvido em conjunto com @Caroline-Camargo para a disciplina de Arquitetura e Organização de Computadores II, desenvolvido no quarto semestre de Ciência da Computação na UFPel

Repository for college course IOAC projects.

Computer Architecture course project

Implementation of a cache memory model through Direct Mapping.

simulating hit/miss behavior of cache memory